Hello, I was wondering if anyone has ever done a triple well layout for an nmos in klayout. I have an nfet that I need to bulk-source tie without grounding it. I've been trying to mess around in klayout for it but haven't quite figured it out. If anyone has an image of how they have laid it out before that would be helpful. thanks!

Which technology?

skywater130

@Amro Tork: In sky130, anything above deep nwell that is inside the nwell perimeter ring but is not nwell is by definition pwell. That is, you don't need to draw an explicit pwell layer (this is opposite of GF180MCU, where the area above deep nwell is automatically nwell unless you explicitly draw a pwell layer).

@Enrique Garcia Does the answer above answer your question? Thanks @Tim Edwards Just wanted to confirm

I think we were able to successfully layout the triple well (passes drc). I didn't realize we didn't need the pwell layer and it was assumed. Having the triple well seems to add an extra net while trying to run LVS called VSUBS, which we think has to do with our vdd tap on the surrounding nwell. Is this the correct way to tap the device, or is it something that needs to be addressed in the schematic?

VSUBS will be the substrate underneath the deep nwell. Make sure you ground the substrate outside of the deep nwell, like surrounding the entire deep nwell area with a substrate guard ring.

Would that still be necessary if other devices in the area are tapped to ground already?

Yes, if you have devices grounding to substrate outside of the deep nwell, that should be sufficient (although I've had times in which I had to drop a contact down to the substrate on the top level of the hierarchy just to make magic's extraction happy).

We found out the solution for our triple well nmos issue. By flattening the entire design, it was able to pass LVS. The recommendation was found in an old thread so we gave it a shot. Thank you so much for the help!