@Tim Edwards When I flatten a layout, the simulation result becomes strange despite the LVS being OK. Why does this happen? LVS clean means that the two netlists are equivalent, so the simulation result should be identical. When I do not flatten a layout, the simulation result is equivalent to that of the original schematic. Here are the SPICE files: • two_layers_neg2_xschem.spice (original netlist) • two_layers_neg2_flatten.spice (netlist of flattened layout) • two_layers_neg2_not_flattened.spice (netlist of hierarchical layout) Thanks in advance.

Do you have ports in your layout? The order of the ports changed between the hierarchical netlist and the flattened netlist.

Thanks for your reply. @Tim Edwards Yes, the .mag file has ports. I found that labels caused this error. If I erase all labels from the flattened mag file other than the ports, the error is gone. Do you know why this happens? Attached files: •

two_layers_neg2_rcx.mag

-> flattened magic file •

two_layers_neg2_rcx_tmp.mag

-> labels are deleted except one (line: 33564). The single label (line: 33564) makes the order of the Vss port move to the last position.