naina singhal
05/15/2024, 9:50 PMLVS, klayout feol, klayout beol
are failing. The LVS check is failing because there is a property error in PNP transistor due to missing "m"
. This was fixed in latest netgen update but the issue is still present while running precheck. Please find the attached reports for klayout feol and klayout beol checks. I do not understand the issue. I have updated my mpw_precheck
folder using make precheck
command and the current version is 4efb33553ee6c2acdb0fa9a6a5f87af099f5c1d5
. Why the klayout drc is failing when magic has a clean drc report in sky 130 process? Please help me with the issue. I have to submit my design in 3rd June chipignite shuttle. Edit : I did find the error using the .xml file and loading marker in klayout. Can you please tell me what are the psdn
and hvi
layer in magic?naina singhal
05/15/2024, 11:26 PMklayout beol
and klayout feol
errors. I am guess that psdn layer is pwell because it looks like that the psubstratediff
and nsubstratediff
layers in magic is tap
in klayout. I could not find the issue in mag file so I directly edited the gds file in klayout to fix psd.2
drc error (though when I opened the gds in magic, I could not see any difference.). Now the only check failing is LVS due to property error in pnp transistor.Tim Edwards
05/16/2024, 12:10 AMPSDN
is an implant layer, and magic generates those automatically. There are several circumstances in which magic will generate improper implant layers, usually due to interactions with layouts that were not done using magic (the most common way to get this to happen is to use standard cells in an analog layout without properly aligning the standard cells in complete rows and columns as they are intented to be placed). There is a way to solve such issues within magic, but your solution of directly editing the GDS in klayout also works.Tim Edwards
05/16/2024, 12:12 AMnaina singhal
05/16/2024, 12:35 AMMitch Bailey
05/16/2024, 3:25 AM