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Hi, we are working on mixed signal design. We crea...
# xschem
a
Hi, we are working on mixed signal design. We created a digital macro and now tried to simulate it in xschem. We don't know proper way to do it. We created a schematic and symbol from verilog netlist using 
make_sky130_sch_from_verilog.awk pwm_generator.v
command and tried to simulate it and facing simulation error.
pwm_simulation.sch
s
@Allwan S Anand creating a spice schematic from a verilog netlist can be tricky. If you post the input verilog file I can do some tests
a
@Stefan Schippers hereby attaching the input verilog file and its generated verilog netlist?
pwm_generator_nl.vpwm_generator.v
s
Following video shows the steps to get a correct schematic for the pwm_generator. You need to include the list of standard cells (something like: 
.include $::SKYWATER_STDCELLS/sky130_fd_sc_hd.spice
) in the teshbench.
sky130_sch_from_verilog.mp4
😎 1
m
@Allwan S Anand Can you share the 
pwm_generator.sym
file?
s
@Mitch Bailey if the script to create sch and sym from verilog is deterministic these should be the sch and sym files. The schematic has been cleaned up by removing tap, decap and filler cells (meaningless for spice) and setting correct power / body (GND, VDD) nets to stdcells.
pwm_generator.schpwm_generator.sym
m
Thanks, @Stefan Schippers. While I agree that the tap, decap, and filler cells are meaningless for spice simulation, if you’re using the spice for LVS, the tap, decap, and filler cells and there connections can be used to ensure that the netlist version matches that layout exactly and that all the cell rows are connected to power.
s
@Mitch Bailey Thank you for pointing out LVS. In this case these cells should be left in. May be these symbols should have the 
format=...
attribute renamed to 
lvs_format=...
so no spice 
format
is defined and these cells will appear only in netlists for LVS comparison.
👍 2
a
Thanks @Stefan Schippers for demonstration. Followed the steps u mentioned and tried to simulate the test bench of pwm_generator. But couldn't do it. it shows below errors. Also hereby attaching the testbench schematic file for your reference.
tb_pwm_generator.sch
s
For some reasons you get all the '?' lines in the netlist. I don't get these. Try to ensure your xschem instalation is the latest one.
Also check voltage source V11, its attributes have syntax errors. Should probably be something like: 
name=V11 value="dc 0 PULSE (0 5 1u 1u 1u 1 1)"
also in the generated pwm_generator.sym change its type to subcircuit
m
@Stefan Schippers maybe this is a mixed signal simulation question. For LVS, I think they should keep the symbol type as primitive and then specify the top level spice and verilog sub modules. But the original question was about calling a verilog module from spice, I think. Currently, the verilog module is not included in the simulation netlist. Does ngspice handle mixed signal simulation?
s
@Mitch Bailey no, ngspice alone does not handle verilog (at least not easily), usually when translating a synthetized design to spice a transistor level simulation is done and the verilog module is simulated after synthesis, as a regular spice subcircuit. Another possibility is to use the symbol as a primitive, get a verilog netlist of the testbench from xschem, set up verilog stimuli and simulate the whole design with a verilog simulator like icarus verilog.
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Thanks @Stefan Schippers Now i solved the netlist error and i can generate netlist correctly but for in case of simulation it shows no job warning and couldn't get output values.Don't know how to solve it ?
tb_pwm_generator.sch
s
@Allwan S Anand I tested your tb_pwm_generator.sch and ngspice did complete the simulation (although there are some warnings about singular nodes, so some additional checks are necessary).
Please send the 
tb_pwm_generator.spice
file so I can test simulation on your netlist.
a
Thanks @Stefan Schippers, hereby attaching 
tb_pwm_generator.spice
file for your reference.
tb_pwm_generator.spice
s
@Allwan S Anand one thing I forgot to mention: you need to regenerate the pwm_generator.sym symbol. For this, descend (select + 'e' key) into the pwm_generator schematic, then press 'a' to create a new symbol pwm_generator.sym, overwriting the old one. return to testbench (control-e) and ensure the pwm_generator symbol is placed correctly.
@Allwan S Anand the following zip file creates a pwm_generator directory. • Expand this zip file (not in a directory where a 
pwm_generator
directory already exists!) • create (if not already existing) a PDK_ROOT variable: 
export PDK_ROOT=/usr/local/share/pdk
(replace the path with the root directory of your pdk install) • export a PDK variable: 
export PDK=sky130A
• Start xschem: 
xschem tb_pwm_generator.sch
• generate netlist and run simulation. I have changed stimuli values to get some meaningful voltage patterns, but please review these since I don't know exactly what the pwm_generator does.
pwm_generator.zip
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Thanks for the help! @Stefan Schippers My simulation setup seems correct now. I can finally run the simulation and analyze the design's characteristics.
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