Hi everyone, I'm working on a scalable binary to one-hot encoding converter circuit in XSCHEM, starting with a 2-bit input to a 4-bit output. My goal is to minimize wiring complexity as I scale this to larger sizes. To achieve this, I've created a custom schematic that integrates a standard AND gate cell from the SkyWater 130 PDK but modifies it to use a single bus input instead of separate inputs for each bit (see picture). This approach should reduce wiring complexity for larger input sizes. Setup: • Inputs: Bus

A[0:1]

• Outputs: Bus

D[0:3]

• Each output is driven by an AND gate requiring specific combinations of inverted and non-inverted inputs. Problem: I'm having trouble when it comes to the two middle AND gates that need to select specific bits from both the inverted and non-inverted input buses. Although I've tried using

bus_connect

and

bus_tap

for this purpose, the resulting netlist doesn't reflect the intended connections, especially for the middle gates. Current Netlist Output:

.subckt decoder_2_dev A[0],A[1] D[0],D[1],D[2],D[3] req_syn req
input_inv[0] A[0] VGND VNB VPB VPWR Ainv[0] sky130_fd_sc_hd__inv_1
input_inv[1] A[1] VGND VNB VPB VPWR Ainv[1] sky130_fd_sc_hd__inv_1
and_0 Ainv[0] Ainv[1] VGND VNB VPB VPWR D[0] sky130_fd_sc_hd__and2_0
and_1 A1[0] A1[1] VGND VNB VPB VPWR D[1] sky130_fd_sc_hd__and2_0
and_2 A2[0] A2[1] VGND VNB VPB VPWR D[2] sky130_fd_sc_hd__and2_0
and_3 A[0] A[1] VGND VNB VPB VPWR D[3] sky130_fd_sc_hd__and2_0
.ends

Desired Netlist Output:

.subckt decoder_2_dev A[0],A[1] D[0],D[1],D[2],D[3]
input_inv[0] A[0] VGND VNB VPB VPWR Ainv[0] sky130_fd_sc_hd__inv_1
input_inv[1] A[1] VGND VNB VPB VPWR Ainv[1] sky130_fd_sc_hd__inv_1
and_0 Ainv[0] Ainv[1] VGND VNB VPB VPWR D[0]
and_1 A[0] Ainv[1] VGND VNB VPB VPWR D[1]
and_2 Ainv[0] A[1] VGND VNB VPB VPWR D[2]
and_3 A[0] A[1] VGND VNB VPB VPWR D[3]
.ends

I have been looking for the way of doing this in the manual but I could not find a solution that works. How can I selectively combine signals from different buses into a new bus? Thanks in advance!

@Mauricio Buendía I may be wrong, but I don’t think spice is going to like comma separated ports in the the subckt definitions. You may be able to fix this by explicitly listing the nets in the symbol format property. In spice, you’ll probably want to prefix all your instance names with an

X

. Spice format specifies that the first letter of a device instance name indicates the type. For bus input, simply try comma separated names attached to the net - I don’t think you need intermediate

A1[*]

or

A2[*]

nets.

Ainv[0],A[1]

and

A[0],Ainv[1]

.

Thanks a lot!

@Mauricio Buendía following image shows the correct way to create a 2 --> 4 decoder in a compact way. First you need inverted A inputs, the 2 inverters

X2[1:0]

do this. The AND gate is placed as a vectored instance

X1[3:0]

and takes all combinations of

A[1],AINV[1] and A[0], AINV[0]

. For the label syntax see https://xschem.sourceforge.io/stefan/xschem_man/tutorial_busses.html

That's very helpful, thank you!