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I am attempting to put verilog logic directly in the top-level `user_project_wrapper.v`, but am running into issues with irdrop analysis during hardening. It’s complaining that vccd2 is unused  (which it is, I’m not using it), and says irdrop check failed. Is there a way to skip irdrop on unused power pins or is what I’m doing completely broken?

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The default user_project_wrapper in the master caravel branch appears to not route power to standard cells (adding verilog logic to the user project wrapper directly causes LVS issues with power pins not being connected to power), but I noticed that the `caravel/verilog/rtl/__user_project_wrapper.v` has logic in the top-level (not in a separate hardened macro like user_proj_example), so I tried to model the openlane configuration after the config.tcl scripts for that design

The `SYNTH_ELABORATE_ONLY": 1,` setting in the default `user_project_wrapper` `config.json` file prevents synthesis and standard cell placement.

You can model the `config.json` file after the one for `user_proj_example` and do synthesis on the top level.

config.json

That worked, thanks! For reference, the final config: