Hi, I was trying to compile the sky130 64x512_8 SRAM using

sram_compiler.py

and it gave me the following error. I also set

netlist_only = True

. The error is not thrown for lower number of words (eg: 16, 32) but occurs for higher values such as 128, 256. Is this a configuration issue or is this a bug? If it is a config issue, perhaps the example file should be changed.

DELAY: Writing stimulus...
ERROR: file simulation.py: line 605: Could not find bl net in timing paths.

This is a bug that is still outstanding

Any way to work around it?

I'm not sure

Is it a regression or do older versions also have the same issue?

I'm not sure

https://github.com/VLSIDA/OpenRAM/issues/228 is it this one?

yes