Hello all, We are facing an issue at post-layout simulation that we don't know how to solve. We have an LDO block with a Miler OTA as error amplifier. @Vicente Osorio (with help from @Daniel Arevalos, @aquiles viza, @Sebastian Sanchez, @Jesus Avila and @Max Vega) tried to do the full post-layout simulation and the results seem completely different to what we get in pre-layout. i.e. the LDO stops regulating as expected. The top post-layout simulation without parasitics works fine, though, which makes us think that the issue comes when we add the parasitics. But, on the other hand, the OTA AC standalone simulations with and without extracted parasitics show similar behavior. Strangely enough, the top LDO simulation with the original schematic OTA vs only replacing the post-layout OTA shows great differences, as seen in the attached figures. We are not sure how to debug this, so your help would be greatly appreciated @Boris Murmann @mehdi @Mitch Bailey @Tim Edwards @Amro Tork @Juan Sebastian Moya @Gabriel Maranhão @Atif Khan

@Jorge Marin Were the post-layout simulation netlists extracted with magic? Are both the netlists with parasitics and without parasitics extracted from the flattened layout? Is the top subckt pin order in both netlists the same?

@Mitch Bailey @Jorge Marin we faced similar kind of issue back in maybe august September. We introduced solution to analog circuits showing different results i.e we were designing opamp with say 70dB gain but in post layout we were getting 40dB. ( I don’t remember we were getting 40 db or nothing)The solution we find was strange on top level we have to put label on a node even we don’t have to make that a pin. We just have to put redundant label to each and every node so that in spice file there shouldn’t be a net that start with # (unnamed node) . While doing pex just remove redundant labels from subckt . After doing that our pex worked as expected. Though it sounds strange but we just had done like that.

dear @Mitch Bailey and @Atif Khan, thanks a lot for your feedback, together with @Vicente Osorio and @aquiles viza we solved this issue with the pin order consideration but thanks also for the other tips, we will keep an eye on that too for the top pex simulation which was also failing