@Mitch Bailey @Tim Edwards @mehdiour chip has 4 latch-up DRC errors

IO.1a2, IO.1b, IO.3a2, IO.3b

that we've been unable to resolve. These errors manifest in diffusion regions connected to analog IO pads, that has a direct connection between the pad and the drain/source of a transistor. Also, they persist even within the ESD protected Analog IO cells. @Amro Tork do you know anything about this type of errors ? Initially, I attempted to address them by including the

Latchup_MK

mask layer to these diffusion regions, as suggested by 14.3.2 I/O Latch-up Related Rules and Guidelines. They wasn't fixed and, in fact, error

IO.3b

only appeared post the addition of this mask. @Atif Khan @Jorge Marin Has any of the other grups encounter these errors? Link to our GDS file: https://github.com/gabrielmaranhao/Bracolin/blob/main/padframe/RING_PAD_BRACOLIN.gds

@Gabriel Maranhão we also have these issues IO.3a2, IO.1b IO.1a2 only . It was interesting to know that latchup_mk has removes these. I will try this. We don’t have IO.3b. Initially we also had IO.3b and some other like IO.1a1_xbutt_xring and IO.3a1_xbutt_xring but are clear after i put guard ring over each well. Does anybody know how we can put latchup_mk using magic or i have to use klayout for that ?

In my understanding the latchup_mk should resolve, but it didn't fixed

@Gabriel Maranhão You need to draw a guard ring around all transistors that are connected to pads. To avoid latch up issues. There are many latchup mitigation designs for the guard ring. I would go with the easiest one for now, a ptap ring around the device that is connected to GND. I assume you are running a commercial tool. If so, I believe you will need to set your VDD and GND names as a parameters in the setup for this to work properly. Please note that I’m talking from memory for the commercial tools. I hope that helps.

@Amro Tork we have place guard ring around all pmos and nmos separately and again guard ring around whole design it solved IO.1a1_xbutt_xring and IO.3a1_xbutt_xring but all other issues are unresolved.

Our design also has a lot of guard rings, but this is interesting:

"need to set your VDD and GND names as a parameters in the setup for this to work properly."

@Atif Khan This would require a deeper analysis. If I had time, I would have been happy to help.

@Amro Tork so can they be waived?

I would waive them yes if the tapeouts are for testing purposes yes.

@Gabriel Maranhão Are your latch-up errors occuring in the

nmos_char

cell? I wonder if adding a small poly resistor between each diffusion and io pad would help.

@Mitch Bailey If the rule was implemented correctly, it will ignore this resistor and highlight. And again, such change would impact the design and it might not work. On the other hand, latch-up has some chance of happening based on the voltage on the supply and signal. And it's design reliability issue that could be ignored if you have proper guard rings around the input transistors.

Including it, yes, but also on other large (2u/2u) transistors

Also as @Gabriel Maranhão mentioned he used latchup_mk layer i tried to use it but issues are not resolved

I saw that the IO Analog pads use this layer on their ESD diodes diffusion

latchup_mk

is a marker layer as the name implies. It has no physical meaning except to guide the rule implementation where to look. And passing it, doesn't mean you are correct either.

Actually I doesn’t have exact idea how to add latch_mk i just placed it following bracolin gds

@Gabriel Maranhão Yes, that's normal. As those are connected to the IO and those designs are made for production not for testing.

So we are just flagging it where to look haha

@Gabriel Maranhão It's not like that.

Ok I will remove them

@Gabriel Maranhão @Atif Khan Good read about Latchup/ESD here: https://www.ti.com/lit/an/slya014a/slya014a.pdf?ts=1715267925022&ref_url=https%253A%252F%252Fwww.google.com%252F

If this is in regards to the

nmos_char

and

pmos_char

cells, there is no nwell guard ring outside the ptap guard ring for nmos (see 10.2) and no ptap guard ring around the nwell guard ring for the pmos (see 10.4). This would be rule

IO.1a2

and

IO.3a2

I can’t see

IO.1b

in the online pdk documetation but it’s probably related to

IO.3b

. These might clear up when you add the guard rings.

Thank you @Amro Tork for those instructions!

Anytime

@Mitch Bailey you are right, due to time constraints I did not add the Nwell/ptap guard ring on this cells. Going to do this today.

@Mitch Bailey can i post you my esd circuit from magic? Maybe you would identify something.

@Atif Khan gds is preferred.

@Gabriel Maranhão i and juan had little meeting in which we have identified latch up error reason. You can discuss with him. I will implement it tomorrow and see how it goes.

I will talk to him, thank you!

@Jorge Marin @Sebastian Sanchez