hello @Gabriel Maranhão and @Atif Khan, we are wondering about the analog pads ESD capabilities the documentation says that the protection is designed for the thick oxide transistors, are you taking any actions to complement this with the extra diodes and poly resistors mentiones here for your chips? https://gf180mcu-pdk.readthedocs.io/en/latest/IPs/IO/gf180mcu_fd_io/analog.html if so, is there any chance for you to share your solutions?

So, we haven't added any more protection to analog PADs, and at first we won't. Even in some circuits I had to remove the ESD structures due to current leakage that interferes with future measurements. This resulted in antenna problems that we are solving by moving metals up and down and I will also add small diodes/resistors in specific cases (connection to the gate).

We have added esd circuit but we are facing drc error. If we can’t resolve these issues in time i am willing to remove these protections circuits.

@Jorge Marin This pad is good enough for most the applications you need. CDM is extra protection you might not need. The pad is already available in the PDK with the ESD diodes. This PAD is designed to support up to 5V. You could use it for lower voltage as well. We have used that pad in our tapeout in GF180MCU.

@Amro Tork thanks for your reply we are actually concerned about this statement, since we have pd connection to regular (non thick-gate) transistors:

@Jorge Marin Thick gates could tolerate higher amount of charges and would serve. This pad provides protection for thick gates. If you put thin gate device, it might break the gates. And your chip manufacturing and production yield might be lower. Meaning the survivability of the chips is less. It doesn’t mean it won’t work. To explain that further, if you produce 100 chips, 90 would be out of production, 10 would fail in the production phase. Out of the surviving 90, 10 would not work due design tolerances, yet still you have 80 working. Out of the 80, 10 would fail due to ESD issues, and ESD poor design. In case of your example, you used those PADs, you most likely lose 20 rather than 10. And you would end up with 60 or 50 working chips. Rest are defective. For research purposes, that’s not even a problem. 10 out 100 working chips is an acceptable norm in publications and research unfortunately. Only in the industry they look at those things. Now, on circuit side, you still could use those pads for 3.3V with no problem. But as mentioned above you will impact yield. The PAD design above is based on HBM model not CDM. Those are ESD modeling/protection techniques. CDM ensures higher yield fundamentally. Instead of losing 50% of your chips, like the example above, you lose 30% of your chips only because you followed CDM requirements. Bottom line, for research, you could remove all ESD protection even if you want. I hope that helps.