open-source-silicon.dev

Or are you going to need higher freqency I/O pads than say 50mhz

Yes, we need an I/O that could go up to 4GHz

We could just add the pads inside the allocated area and get bare dies and characterize the design from those pads and ignore the normal I/O pads entirely 

FWIW if you just want to verify if the PLL is actually working rather than its complete performance, you could use some prescalers to divide down the PLL's output to the PADs frequency range.

You would be able to characterize the frequency of PLL but not other characteristics like phase noise, etc…

We'd want to characterize jitter if we want to use it for real uses

<@U01EK2VDMDG> I just talked to <@U06H50VMDPU> about how to get a full chipignite run. Do you have anything that will produce a GDS of the PLL?

<@U017B06CK3K> The GDS already there: <https://github.com/mabrains/PLL_design/tree/main/pll_int/PLL/layout|https://github.com/mabrains/PLL_design/tree/main/pll_int/PLL/layout>

But again this PLL needs a detailed review.

The fractional version was not integrated