open-source-silicon #serdes

Yeah. So in that case, perhaps the best option to avoid any gearboxing would be to design the actual SERDES with a 10:1 serialization ratio, and have the parallel side be 10 bits at 250 MHz

Andrew Zonenberg

12/09/2021, 6:28 AM

Which you can then hook up to an 8B/10B encoder (feeding it 8 data bits plus a K/D bit) or 10 bits of arbitrary data for using other line codes

Andrew Zonenberg

12/09/2021, 6:30 AM

Or 20 bits at 125 MHz, but that might be harder to write control logic for because you have the potential for a TLP to start at an even or odd symbol within the 2-symbol block

Arman Avetisyan

12/09/2021, 8:40 AM

The problem is not the TX part, it's the RX part

Arman Avetisyan

12/09/2021, 8:40 AM

The need for PLL, Clock Data Recovery, etc

Arman Avetisyan

12/09/2021, 8:40 AM

130nm is perfectly capable of PCIe Gen 1

Arman Avetisyan

12/09/2021, 8:42 AM

For people who are designing TX, High Density Flip Flop is not capable of 2.5GHz, so probably will need to use the _hs one

Arman Avetisyan

12/09/2021, 8:43 AM

Also: NGSPICE cant draw frequency grapth of frequency vs control voltage. So probably will need to find a different way, maybe use "meas" and "alter" ngspice commands

Andrew Zonenberg

12/09/2021, 2:41 PM

Well we need a PLL for TX too

Andrew Zonenberg

12/09/2021, 2:43 PM

For RX, you don't strictly have to do a CDR PLL. You can also oversample (which doesn't require super fast clock rates - you can use multiple phases of one clock, then some CDC logic to phase shift 1/4 cycle at a time). not saying this is the best strategy but it can be done

Andrew Zonenberg

12/09/2021, 2:43 PM

see Xilinx XAPP523 for an example of how this has been done in FPGA

Andrew Zonenberg

12/09/2021, 2:44 PM

But if we can build a good phase detection circuit and a regular PLL, a CDR PLL probably won't be that much more work

Andrew Zonenberg

12/09/2021, 2:47 PM

An initial proof of concept RX could be done with the same PLL we use for TX and the 4x oversampling approach though

Andrew Zonenberg

12/09/2021, 2:48 PM

The fun part of RX IMO is adding things like equalization

Andrew Zonenberg

12/09/2021, 2:48 PM

TX side pre/deemphasis is straightforward

Andrew Zonenberg

12/09/2021, 6:30 PM

For RX we can probably get away with a simple CTLE though at typical PCIe ranges and gen1 speeds

Andrew Zonenberg

12/09/2021, 6:30 PM

no need for a fancy DFE

Troy Benjegerdes

12/10/2021, 7:19 PM

so has anyone taped out a > 1ghz PLL on any of the MPW-1/2/3 shuttles yet?

Troy Benjegerdes

12/10/2021, 7:24 PM

I like the oversampling approach for a quick prototype. So just as an academic experiment, what if we wanted to do some kind of PAM4 modulation and DSP of the samples, would we be able to do something like what 100Gig transceivers are starting to use now?

yrrapt

12/10/2021, 7:27 PM

https://github.com/yrrapt/caravel_amsat_txrx_ic https://github.com/yrrapt/caravel_amsat_txrx_ic_mpw2

mehdi

02/11/2022, 8:57 PM

@User Please take a look here

Ted

05/12/2022, 10:26 PM

@User has left the channel

Michael Strothjohann

11/05/2022, 6:33 PM

@Michael Strothjohann has left the channel

Tim Edwards

12/12/2022, 2:04 PM

@Tim Edwards has left the channel

Dan Fritchman

12/14/2022, 11:02 PM

Linking from #analog-design - https://open-source-silicon.slack.com/archives/C016HUV935L/p1670865913046049 A talk primarily about our OSS analog-design tools, but (at the end) featuring their use in ongoing SERDES work

Anagha

12/19/2022, 8:12 AM

@Anagha has left the channel

Philipp Gühring

03/18/2023, 12:29 PM

https://www.linkedin.com/posts/tony-chan-carusone-2799a38_introduction-to-serdespy-activity-7042449496282169344-QOTx?utm_source=share&utm_medium=member_android

Philipp Gühring

03/18/2023, 12:30 PM

https://youtu.be/FPr4emBE7fo▾