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#serdes
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Troy Benjegerdes
12/09/2021, 4:12 AM8b/10b and 2.5Ghz (for Infiniband SDR or PCI-express gen1) seems like the first thing we should try for, and may be achievable on SKY130 - a
Andrew Zonenberg
12/09/2021, 6:28 AMYeah. So in that case, perhaps the best option to avoid any gearboxing would be to design the actual SERDES with a 10:1 serialization ratio, and have the parallel side be 10 bits at 250 MHz - a
Andrew Zonenberg
12/09/2021, 6:28 AMWhich you can then hook up to an 8B/10B encoder (feeding it 8 data bits plus a K/D bit) or 10 bits of arbitrary data for using other line codes - a
Andrew Zonenberg
12/09/2021, 6:30 AMOr 20 bits at 125 MHz, but that might be harder to write control logic for because you have the potential for a TLP to start at an even or odd symbol within the 2-symbol block - a
Arman Avetisyan
12/09/2021, 8:40 AMThe problem is not the TX part, it's the RX part - a
Arman Avetisyan
12/09/2021, 8:40 AMThe need for PLL, Clock Data Recovery, etc - a
Arman Avetisyan
12/09/2021, 8:40 AM130nm is perfectly capable of PCIe Gen 1 - a
Arman Avetisyan
12/09/2021, 8:42 AMFor people who are designing TX, High Density Flip Flop is not capable of 2.5GHz, so probably will need to use the _hs one - a
Arman Avetisyan
12/09/2021, 8:43 AMAlso: NGSPICE cant draw frequency grapth of frequency vs control voltage. So probably will need to find a different way, maybe use "meas" and "alter" ngspice commands - a
Andrew Zonenberg
12/09/2021, 2:41 PMWell we need a PLL for TX too - a
Andrew Zonenberg
12/09/2021, 2:43 PMFor RX, you don't strictly have to do a CDR PLL. You can also oversample (which doesn't require super fast clock rates - you can use multiple phases of one clock, then some CDC logic to phase shift 1/4 cycle at a time). not saying this is the best strategy but it can be done - a
Andrew Zonenberg
12/09/2021, 2:43 PMsee Xilinx XAPP523 for an example of how this has been done in FPGA - a
Andrew Zonenberg
12/09/2021, 2:44 PMBut if we can build a good phase detection circuit and a regular PLL, a CDR PLL probably won't be that much more work - a
Andrew Zonenberg
12/09/2021, 2:47 PMAn initial proof of concept RX could be done with the same PLL we use for TX and the 4x oversampling approach though - a
Andrew Zonenberg
12/09/2021, 2:48 PMThe fun part of RX IMO is adding things like equalization - a
Andrew Zonenberg
12/09/2021, 2:48 PMTX side pre/deemphasis is straightforward - a
Andrew Zonenberg
12/09/2021, 6:30 PMFor RX we can probably get away with a simple CTLE though at typical PCIe ranges and gen1 speeds - a
Andrew Zonenberg
12/09/2021, 6:30 PMno need for a fancy DFE - t
Troy Benjegerdes
12/10/2021, 7:19 PMso has anyone taped out a > 1ghz PLL on any of the MPW-1/2/3 shuttles yet? - t
Troy Benjegerdes
12/10/2021, 7:24 PMI like the oversampling approach for a quick prototype. So just as an academic experiment, what if we wanted to do some kind of PAM4 modulation and DSP of the samples, would we be able to do something like what 100Gig transceivers are starting to use now? - y
yrrapt
12/10/2021, 7:27 PM - m
mehdi
02/11/2022, 8:57 PM@User Please take a look here - t
Ted
05/12/2022, 10:26 PM@User has left the channel - m
Michael Strothjohann
11/05/2022, 6:33 PM@Michael Strothjohann has left the channel - t
Tim Edwards
12/12/2022, 2:04 PM@Tim Edwards has left the channel - d
Dan Fritchman
12/14/2022, 11:02 PMLinking from #analog-design - https://open-source-silicon.slack.com/archives/C016HUV935L/p1670865913046049 A talk primarily about our OSS analog-design tools, but (at the end) featuring their use in ongoing SERDES work - a
Anagha
12/19/2022, 8:12 AM@Anagha has left the channel - k
Kennedy Caisley
07/25/2023, 6:04 PM@Kennedy Caisley has left the channel