<!channel>: Chipalooza participants: I now have two days to finish the layout of the test chip for the April shuttle. I think most designers know where they stand and whether or not they are going on the April tapeout. However, there are a couple of borderline cases, so here is the list I have of projects on my test chip:

Brady Etz

Luis Henrique Rodovalho

Thomas Dexter

Lucas Franck

Jorge Marin

Or Dicker

Andrew Kang

Tamas Hubai

Robin Tsang

There are also a number of designers who are close to done but have indicated that they will miss the deadline for one reason or another, and will go out on another test chip on the June shuttle run. For those designers above: I have just pulled a fresh update of all the repositories. I consider the state of every repository to be frozen as of now and will not do another pull before tapeout unless you contact me and indicate otherwise. If you have any serious concerns about the state of the IP, also let me know.

For the rest of us: Can we track your progress combining circuits no one else has connected before in real time?

In the end, all I want is the 10 uA biasing current I was promised. Appendices are only for documentation freaks who care about destroying the mystery of analog circuits. If everyone knows how to design those circuits, how can I tell myself I'm better than them?

Too much is currently in flux to give out any useful information about it, but in a couple of days (i.e., prior to the shuttle run deadline), it will be posted into a publicly-accessible repository, probably github/efabless/chipalooza_projects_1/. But don't go looking for it yet, as it's still only local on my desktop.