Thomas Dexter
04/21/2024, 8:38 PMTim Edwards
04/21/2024, 9:37 PMnetlists/rcx/
, and it will get used.
The things that I understand can be very helpful: (1) Switching to ngspice's KLU solver; (2) Making "reltol" and "abstol" much bigger; (3) Setting the extresist tolerance to a very low number like 0.001 in magic.
I would recommend running a simulation with the simple layout-extracted netlist with no parasitics to make sure there are no issues resulting from a pin order mismatch between the schematic and layout netlists. If your results look meaningful but just the simulation is slow, then the pin order is probably fine and some of the tweaks suggested above may help.
You do not necessarily need or want to run every simulation on every corner condition with the R-C parasitics; you can get a ballpark idea of what percentage degradation you're getting from the layout parasitics with a single simulation at typical.