I have a question having two clocks on my design. ...
# timing-closure
m
I have a question having two clocks on my design. The second clock is generated from the main clk with a simple prescaler to run some part of the circuit slower. If I specify only the main clock in openlane I get a lot of "unclocked register/latch pins" from the sta check report I tried adding this to the .sdc (googling about about the subject, don't know much about sdc constraints):
create_generated_clock -name clk_12mhz -source [get_ports $::env(CLOCK_PORT)] -divide_by 4 [get_nets u_usb_cdc_devices.clk_12mhz]
It seems it worked. I don't get the warnings and it uses clock buffer on those nets now. I wanted to know if that was the correct way of doing it. Here's an image of the design's clock nets with and without that constraint
m
It sounds right to me
👍 1
t
Hi Matt, it's been a while since I've been here, so your answer suggests, that the flow now supports multi-clocks, right ? And even internal clock roots ?
m
The is not an internal clock root, it is a generated clock where the root is
-source [get_ports $::env(CLOCK_PORT)]
.
I'm not sure what "multi-clocks" means but we have always supported multiple clocks in OpenROAD
t
I was under the impression, that clock tree synthesis only supported one clock. I remember it has been discussed here. But I might also be wrong. Sorry for that, Cheers !
m
No it supports multiple clocks (the trees are all independent)