Maximo Balestrini
04/19/2024, 1:14 PMcreate_generated_clock -name clk_12mhz -source [get_ports $::env(CLOCK_PORT)] -divide_by 4 [get_nets u_usb_cdc_devices.clk_12mhz]
It seems it worked. I don't get the warnings and it uses clock buffer on those nets now.
I wanted to know if that was the correct way of doing it.
Here's an image of the design's clock nets with and without that constraintMatt Liberty
04/22/2024, 11:47 PMTobias Strauch
04/30/2024, 7:17 PMMatt Liberty
04/30/2024, 9:19 PM-source [get_ports $::env(CLOCK_PORT)]
.Matt Liberty
04/30/2024, 9:19 PMTobias Strauch
05/01/2024, 8:19 PMMatt Liberty
05/01/2024, 8:20 PM