Hi , I am making a hierarchical design in magic. the design consists of three subckts named fd. as shown below. Wiring in one subckt reflected the wiring in other subckts also. this was time saving. but this was not helping while labelling. Labels are also copied in all subckts. I want to uniquely label my subckts so that there is no short between wires. How can I do that?

When you use hierarchy, Magic will automatically append the identifier for the subcircuit before the net label (in the flat layout). In this example flattened layout, Magic keeps a top-level label

dout_filt

, but it has created a lower-level label

x7.x2.x3.CLK

, which is the

CLK

net inside a standard cell named

x3

inside a subcircuit named

x2

inside a subcircuit named

x7

. When you extract a spice netlist for LVS or simulation, the highest-level label will prevail. In this layout

dout_filt

overrides

x7.clkout

when they are connected.