Hello! Has anyone tried synthesizing an inverter-based clock tree in the CTS stage in the OpenLane flow ? • I have a design where I ran the OpenLane flow with the default CTS settings initially, and post-CTS simulation is matching the RTL functional sim. ◦ CTS_ROOT_BUFFER:

sky130_fd_sc_hd__clkbuf_16

(Default) ◦ CTS_CLK_BUFFER_LIST:

sky130_fd_sc_hd__clkbuf_8 sky130_fd_sc_hd__clkbuf_4 sky130_fd_sc_hd__clkbuf_2

(Default) • In the next run, I kept: ◦ CTS_ROOT_BUFFER same as before:

sky130_fd_sc_hd__clkbuf_16

◦ Changed CTS_CLK_BUFFER_LIST to:

sky130_fd_sc_hd__clkinv_8 sky130_fd_sc_hd__clkinv_4 sky130_fd_sc_hd__clkinv_2

With these changes, the OpenLane flow has completed successfully with only max_slew violations (only marginal violations and can be ignored) However, post-CTS simulation is now having mismatches with the RTL functional sim. But Post-Placement (pre-CTS) simulation is matching with RTL sim, implying that the mismatch was caused after the CTS stage.

If you tell the tool that an inverter is a buffer you can't expect it to work, they are not the same thing