What are "3.0V/5.0V native NMOS FET" exactly ? Looking at the data in the PDK doc they seem to have an almost 0 threshold ?

https://en.wikipedia.org/wiki/Native_transistor I don't have sources, but once I've heard that all bulk planar topologies have native transistors. The conventional NMOS must pass for a extra doping process. The native ones are nmos ones with a mask to avoid the extra process. They are really hard to work with as, normally, you can't use them as in the diode configuration in current mirrors, for example. And you can't make a good inverter with it because there are no PMOS native transistors, so the thresholds are too unbalanced.

Oh doh, I didn't even thing to google, I didn't think "native" was like a actual term, I thought it was just a name in the sky130 pdk.

By the way, native transistors, or zero-VT transistors are something like depletion mode FETs. Before CMOS, digital circuits were only NMOS or PMOS, not both, so you had to use only one kind of doped transistors. It is a good read and rabbit hole. https://en.wikipedia.org/wiki/Depletion_and_enhancement_modes

Yeah, I knew about depletion modes ones, I've actually used discrete ones as current sources in some circuits, but didn't know "native" ones.

Phil Allen noted that the 5V NVT FET in series with a regular Vt NFET, with both gates tied together, makes an excellent cascode not requiring any bias voltage. I've been wanting to run that in simulation and post the resulting I-V curve, but I haven't had the time to do it.

https://patents.google.com/patent/US6211659B1/en This patent shows the use of the self cascode current mirror with dual VT. It also shows several configurations of body biasing to improve current mirrors. When I thought about it on my own in 2020, I thought I was making a real discovery... Nothing new under the sun.

In the online doc, the device is shown in a pwell inside a deep-nwell, but can you also make it directly on p-substrate ? The wikipedia article suggest yes, but of course not sure if that's allowed in sky130.

@tnt: The device does not need to be in deep nwell.

maybe I'm wrong, what I understood in my career in semiconductor is that native or zero-Vth devices are good for differential pair design (input stage for operational amplifiers); likely because zero Vth