Hi, again. I have a problem performing LVS over the top analog layout block. A classic

Top level cell failed pin matching

in which both top level devices classes are equivalent. Maybe it's something easy to fix, but I have not figured where is the problem in the layout .

Subcircuit summary:
Circuit 1: SDC_clean                       |Circuit 2: SDC                             
-------------------------------------------|-------------------------------------------
ARRAY_RES_ISO (1)                          |ARRAY_RES_ISO (1)                          
INTERNAL_SDC (1)                           |INTERNAL_SDC (1)                           
ARRAY_RES_HIGH (1)                         |ARRAY_RES_HIGH (1)                         
Number of devices: 3                       |Number of devices: 3                       
Number of nets: 7 **Mismatch**             |Number of nets: 8 **Mismatch**             
---------------------------------------------------------------------------------------
NET mismatches: Class fragments follow (with fanout counts):
Circuit 1: SDC_clean                       |Circuit 2: SDC                             

---------------------------------------------------------------------------------------
Net: VSS                                   |Net: VSS                                   
  INTERNAL_SDC/VSS = 1                     |  INTERNAL_SDC/VSS = 1                     
  INTERNAL_SDC/REF_IN = 1                  |                                           
  ARRAY_RES_HIGH/IN = 1                    |                                           
                                           |                                           
(no matching net)                          |Net: REF_IN                                
                                           |  INTERNAL_SDC/REF_IN = 1                  
                                           |  ARRAY_RES_HIGH/IN = 1                    
---------------------------------------------------------------------------------------
Netlists do not match.

Subcircuit pins:
Circuit 1: SDC_clean                       |Circuit 2: SDC                             
-------------------------------------------|-------------------------------------------
N2_R                                       |N2_R                                       
VDD                                        |VDD                                        
DOUT                                       |DOUT                                       

VSS                                        |(no matching pin)                          
(no matching pin)                          |VSS                                        
VSS                                        |(no matching pin)                          
---------------------------------------------------------------------------------------
Cell pin lists for SDC_clean and SDC altered to match.
Device classes SDC_clean and SDC are equivalent.

Final result: Top level cell failed pin matching.

Pin mismatches are meaningless if a cell has not passed a topological check. The "NET mismatches" is a simple case of "VSS" and "REF_IN" on the right side matching only "VSS" on the left side. This implies that in your layout, you have shorted REF_IN to VSS. Once the nets match, I would expect the pins to match also.

Your extract output may also indicate that the nets are shorted.

I'm not sure why this problem happens, klayout connectivity report (after fixing lyt file) reports VSS and REF_IN as two separate networks. don't know how to find the shorted networks. • In klayout interface I don't have all connectivity rules on the lyt files, maybe there's something important? taps or diff should be considered as connections? • In the same track, I specified that

poly.res(66/13)

remove

poly(66/20)

connectivity. I assume that's correct because ARRAY_RES_HIGH passes LVS with two ports. • Does magic have a tool similar to "Trace all nets"? Does pressing constantly "s" follow the connectivity between layers? • The image shows

SDC

connections, top module just have 4 (None of which is VSS), so the problem should be deeper on the hierarchy but all the underlying cells are lvs clean.

<connectivity>
  <connection>poly,66/44,li</connection>
  <connection>li,67/44,met1</connection>
  <connection>met1,68/44,met2</connection>
  <connection>met2,69/44,met3</connection>
  <connection>met3,via3,met4</connection>
  <connection>met4,via4,met5</connection>
                                             <!--Should diff, taps be considered in connectivity?-->
  <symbols>poly='66/20+66/5-66/13'</symbols> <!--Here I remove connectivity when poly.res is over poly-->
  <symbols>li='67/20+67/5'</symbols>         <!--Which layers should be considered? drawing, label. David indicates short.-->
  <symbols>met1='68/20+68/5'</symbols>
  <symbols>met2='69/20+69/5'</symbols>
  <symbols>met3='70/20+70/5'</symbols>
  <symbols>via3='70/44-89/44'</symbols>
  <symbols>met4='71/20+71/5'</symbols>
  <symbols>via4='71/44-97/44'</symbols>
  <symbols>met5='72/20+72/5'</symbols>
 </connectivity>

Yes, pressing "s" several times or using the "select net" command in magic does a connectivity check.

@aquiles viza there is the possibility of diffusion, well or substrate shorts. However, because of the number of

licon

that may not be practical in klayout. If you add tap/diff, be sure to subtract poly.

@aquiles viza: Now that I've had a chance to download and look at your GDS file, I can see that

ARRAY_RES_HIGH

has the resistors shorted to the substrate. That's fine for the dummy resistors on the sides, but the central resistor is connected to the tops of the dummy resistors, and from there to the substrate. If you disconnect the top of the middle resistor from the resistors on the side, it will no longer be shorted, although you need to bring in your ground connection from somewhere.

Acording to schematics, the bulk of the resistors is connected to SENS_IN / REF_IN. With Jorge both agree in changing it. But I don't think this is related with the REF_IN and VSS short problem we have.

Yes, it is, because in the layout the "bulk" of the resistors is a substrate contact connecting directly to the substrate.

I'm going to fix this right now

This would work with either an nwell or a pwell in deep nwell under the resistor. There's no need for a deep nwell here, so just an nwell should do the job, with the nwell tap connected to REF_IN.

Understood, I will put an "nwell grid" to fill the space between resistors. This problem of not recognizing p-resistors has caused by the hierarchy, if I flatten the device magix extraction writes an empty subckt. ARRAY_RES_ISO should have bulk connected to VDD or is not necessary?

The nwell around the array resistors should be at or above the highest voltage on any resistor in the array, to prevent the pwell from forward-biasing into the nwell and deep nwell.

Circuits match uniquely.

Thanks David and Tim. In which file of magic are defined the connectivity rules?

In the tech file (e.g.,

sky130A.tech

), section

connect

.