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<@U0169AQ41L6> the chip top DRC on Klayout is taking too long, over 30 hours, and my PC crashed. Also, we lost power at the University on a second time. Is there any chance we could access Google's machines? LVS will probably take this long too...

Hi Gabriel - Are you in Juan's team? if so, then he has resources to run that. If not, let's schedule some time tomorrow where I can add you to GCP

Hi <@U0169AQ41L6>, we are both working on the same chip (Bracolin), but we're not on the same team. Juan is currently finishing the SAR-ADC. It would be good to begin executing the DRC and LVS for the chip top, as these processes are time-consuming. So, scheduling a time tomorrow to do so would be nice, if possible.

Can you try to join now:
Openfasoc Weekly meeting
Friday, April 19 · 10:00 – 11:00am
Time zone: America/New_York
Google Meet joining info
Video call link: <https://meet.google.com/vzy-gjdy-rbc>
Or dial: ‪(US) <tel:+1650-667-2505|+1 650-667-2505>‬ PIN: ‪854 357 839‬#

I'm going to the University, I will join in 10min

<@U0169AQ41L6>: I've uploaded the PDK files using Volare and configured everything to run the DRC. I noticed that there are 60 cores available, so I've set KLayout to use 30. Currently, I'm running the DRC for an alpha version of the BRACOLIN chip top. It's been 40 minutes, and it's still running. I'll update you once it finishes.

50h and still running, it is a full complete DRC (antenna+density). I think Klayout is not optimized for parallel processing, it starts using a lot of cores, then it reduces to a few (2 or 3). The amount of vias on the metal rail of the I/O cells makes the DRC extremely slow... lets see if Monday it finishes....

I think he is the maintainer of KLayout. There should be a KLayout channel where you can ask

<https://open-source-silicon.slack.com/archives/C01DH7SPX41/p1713828027463209>

Good news, was using the flat option, and that's for final final version... going to use deep mode from now on.