Hi All, I want to trace few resistances from my pe...
# analog-design
n
Hi All, I want to trace few resistances from my pex netlist (screenshot attached) to the layout. I want to see which connection is causing these parasitic resistances. Is there any way to do that in magic? Thank you.
t
It's not particularly easy to trace the resistive network. The
.res.ext
file used to define the additional nodes and resistors has some coordinate information in it that can be used to figure out roughly where one of the internal network nodes is.
n
@Tim Edwards I am driving around 20mA out of one big mosfet and the VSS voltage peaks up to 0.6V after parasitic extraction which messes the circuit completely. I am just tryin to see what resistance is causing huge voltage drop in VSS. Is there any other way to figure it out? I have routed VSS in metal3.
t
0.6 / 20E-3 = 30, so you only need 30 ohms resistance to draw down the supply voltage by 0.6V. How many contacts are on the FET? Contacts to diffusion are around 600 ohms each (840 on the high corner), so an array of 20 contacts is by itself 30 ohms.
n
@Tim Edwards Thanks a lot for your answer. I have a 600um wide transistor. It is divided into 2x30x10. So there are 30 fingers, each with 10um width and at end two multipliers.
I am routing the diffusing (source) up to metal3. I guess stacking vias should reduce the resistance. Isn't it?
I am getting the vss voltage results from vss.t nodes in pex simulation.
I am attaching the gds of the transistor. If possible please look into it. Thank you.
t
The substrate connection isn't labeled, so I don't know where you are connecting to it. But the problem here isn't the FET sources and drains; your FET is connected between two large buses with plenty of contacts. All of that is fine. But your bulk connection is just a tiny ring of highly resistive local interconnect around the perimeter. That's fine if you make a solid connection to ground on all sides. But if you connect ground to only one point, then the other side is about 300 squares of 12.5 ohms/square local interconnect, which is about 3.5 kOhms. The substrate itself is about 4.4 kOhms across, so there's about 2 kOhms resistance from corner to corner on the substrate under the device.
n
Thank you so much for help @Tim Edwards. It worked and ground resistance is around 2 ohm now.
Hey @Tim Edwards sorry ... one more question. I have around 2000 vss nets after parasitic extraction in my other design. Is there any way to merge them together to calculate the overall ground resistance?
t
You can use various values of
extresist tolerance <value>
to (possibly) get a coarser resistance network. However, magic already does resistance network reduction, so it's really a deep algorithmic problem. Commercial tools do a somewhat better job of network reduction. If you want to get a single value of resistance, the "lumped" resistance model in magic may tell you what you want; don't do a full R-C extraction, but do a normal extraction and then run
ext2sim rthresh 0; ext2sim
, which should produce a .sim file with an entry
r vss <value>
that is a single resistance value for the entire
vss
network.
n
@Tim Edwards I am getting a value of R = 277794 for VSS net. This should not be the case since the current through the circuit is 19mA and simulation shows a ground potential of around 60mV.
What are the units of R and C in .sim file? The file says units: 500000.
t
R should be in ohms, and C should be in femtofarads. The "units" line only applies to values which are physical dimensions (such as transistor L and W).
n
Ok. Then .sim file shows a VSS resistance of 277.794kohm.