Hi, I am working on a SPI input for digital configuration of an analog chip. Since the logic is minimal, we are manually placing the digital blocks. When working with blocks such as inverters, NANDs, and NORs, simulation set-up and execution take very little time. However, after adding 15-20 standard-cell flipflops (dfsbp_1), the simulation setup takes several minutes to complete. This is pretty crazy for a testbench with fewer than 50 standard cells in it. Are there any known issues similar to this, or debugging steps I can take? I have already tried reducing timing tolerance and increasing timestep. These steps did not help. Have not seen any similar issues with standard cells in sky130 before, so I think the flip-flops are likely the issue.

Flip flops are usually a problem for initial conditions, as they are bistable. You should run your transient sims with UIC, so all nodes are initialized to 0. Setup time will be zero this way. Another solution is to initialize the flip flops to a known signal. You could set/reset them in the initial time, if they have pins for that. If they don't have pins, you could manually enter their initial conditions with a .uic statement in the spice testbench.

That makes sense. I tried various combinations of UIC and signal definitions. • SET_B = 1 leads to outputs going to VDD, so that should lead to a rapid setup time if just using initial conditions. However, setup time remains the same • UIC in the transient statement also does not change setup time • .ic used to set all dfstp_1 inputs to VSS/VDD does not change setup time either (this is with SET_B = 0, to allow standard operation) My current testbench only has 5 flipflops, and takes 30-35 seconds to setup.

Are you using a .spiceinit file? It should look like this.

* ngspice initialization for sky130
* assert BSIM compatibility mode with "nf" vs. "W"
set ngbehavior=hsa
* "nomodcheck" speeds up loading time
set ng_nomodcheck
set num_threads=2

No, I don't think so. Just using xschem "code shown" blocks. These add control code directly into a single file during netlisting

.include spi_parallel.cir

.param V_IO_DIG = 3.3

.param reg_reset_v = 0

.param VPWR = 1.8

.param VGND = 0

.ic v(reg_reset)=0

.option savecurrents

.tran 10n 1.1u  uic                     ; this must be enabled when writing raw file/graph

.save all

.control

save all

write SPI_test.raw                                    ; used to write values to be loaded on graph

.endc

Try it. Make a .spiceinit file and place it in you simulation folder. Just see where you netlist is saved.

That worked! Through a little bit of experimenting, it looks like the key line is:

set ngbehavior=hsa

Many thanks @Luis Henrique Rodovalho