Hi <@U01QTMG2K8R> as suggested by you I have updat...
# magich
Himanshu Singh
04/12/2024, 11:27 AMHi @Luis Henrique Rodovalho as suggested by you I have updated by pfd layout. there are tap cells provided in the extreme right of every row and cells have been arranged within power and gnd rails. can you suggest anything else i am missing out ?
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Luis Henrique Rodovalho
04/12/2024, 11:28 AMExtract the netlist and share it with us, so I can see if its functional
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Mitch Bailey
04/12/2024, 11:36 AM@Himanshu Singh I can’t tell from this layout, but do all of the nwells have an ntap connection or just the far right ones?
You can connect all the nwells by placing an nwell region in the parent hierarchy.
Make sure you have ntaps and ptaps at least every 15um.
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Himanshu Singh
04/12/2024, 11:52 AMActually it's not working. I have connected all nwells as suggested by @Mitch Bailey and sending the spice files for the updated design.
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Luis Henrique Rodovalho
04/12/2024, 11:55 AM.subckt pfd_lay f_clk_in up VPWR VGND down f_vco
Xx1 VGND VGND VGND VGND VGND VGND VPWR VPWR x9/B sky130_fd_sc_hd__nand4_1
see this line from your spice. it seems there is a short there. a very big one
Luis Henrique Rodovalho
04/12/2024, 12:00 PMGo to your layout, put your cursor over a signal route, and press 's'. You can press more times to see where the route is connected. This way you can inspect if there are shorts. You can erase some parts of the metal tracks to isolate it in segments, and find the short.
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Himanshu Singh
04/12/2024, 2:20 PMthanks for the insight. i had labelled all 4 inputs with the same name. got the correct output now