Even though I'm delaying layout to avoid having to deal with moving PDK and design tool targets, one question seems to show up several times, redundantly, in this discussion forum: Specific challenge requirements All designs must be in deep nwell Deep nwell should be surrounded by psub guard ring Putting everything into a deep nwell (including shallower pwells for nfets) is a precautionary measure to isolate individual building blocks as <ahem> well as possible from mutual interference. Been there, done that (XFAB CX08 HV), became one of these conspirators who implanted chips into other people. Is this the intention of the challenge requirement: as few components as possible connecting to substrate, so building blocks that misbehave can be junction isolated from the rest of the chip? And how are antenna rules about substrate and well taps supposed to be handled??