If I have a digital route in my circuit routed by ...
# chipalooza
r
If I have a digital route in my circuit routed by Openlane, is that required to be in a DNW? The circuit is top-level DRC/LVS clean but the digital route is not in DNW and I just want to ask ahead of time. Also, level-shifters from the sky130 library cannot be inside a DNW because it shorts out the hi/low supplies.
c
Is it possible to define a pwell in a deep nwell, and (shallower) nwells in the pwell? If so, what well and substrate connections are required?
m
Inside a deep nwell, all nwell is shorted (to the deep nwell).
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t
@Robin Tsang: Yes, I suggest putting all digital outside the deep nwell structure. I have an example of a (very poor) crystal oscillator design (which I stopped working on after adding the crystal oscillators to the list of IP for Chipalooza) that does just that, with the final digital buffer stage sitting outside the deep nwell: https://github.com/RTimothyEdwards/sky130_ef_ip__xtal_osc_16M.
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@Robin Tsang: You'll note in that design that I made my own level shifters, and they are split across the deep nwell boundary.
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r
Thanks Tim. Also, for a pnp bipolar, do you want it inside a DNW? In the circuit where the pnp is used, the base (nwell) is connected to ground. So if the pnp is inside DNW, the DNW has to be grounded as well instead of being connected a positive supply, as they are shorted structurally.
Right now, the pnp is in its own DNW tub connected to ground.
t
Having a separate DNW tub sounds like the right solution here, even though it's going to take up a lot of area.
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r
Tim, not a priority item, just a nice to have. When creating an "nwell region with guard ring" using the Magic pcell generator, there are two discontinuities in the
nsubstratediff
layer (see picture) causing DRC errors. It will be nice having a pwell version as well, and I understand the whole structure can be easily flipped by drawing pwell over nwell. My use case is drawing the p-type guard ring around nfets that are instantiated without a guard ring, so transistors of different sizes can be packed closer together.
t
That looks like an unintentional arithmetic error.
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Okay, thanks for that catch. Somehow a
popbox
line got deleted out of the recipe by accident. Easily fixed!
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I have added menu items for 1.8V and 5.0V substrate guard rings, and a menu item for a 5V nwell guard ring. I need to consolidate that into a single dialog window allowing various selections of double/triple rings and low/high voltage, and selecting the width of the guard ring diffusion. But it's better than before.
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c
@Tim Edwards, give me a holler once your guard ring dialog is a fixed enough target that I should update my tool chain (detailed instructions will help a lot) and start my actual layout. An example worked out layout that shows nested wells, guard rings, and taps for antenna rules, and demonstrates the extraction and verification flow will save a lot of folks in it for the t-shirt a lot of time and effort.
@Tim Edwards, an example layout that shows everyone how to draw the structures by hand, in case your tool is buggy, will be particularly helpful.
r
Thanks a bunch Tim!