Hello @Tim Edwards , @Tim 'mithro' Ansell If I want to tape-out a design using sky130_fd_sc_hd SCL using the OpenLane flow, which are the PVT corners for which I must mandatorily close the timing ? If I do not set

LIB_SLOWEST

&

LIB_FASTEST

variables in the config file, OpenLane by default seems to be setting:

Slowest: ss_100C_1v60
Fastest: ff_n40C_1v95

LIB_TYPICAL is set to tt_025C_1v80

I was told by @Kunal that the ss_* corner lib files were having some issues due to the sky130 OpenPDKs being optimized only for the tt_* corners. But he had also mentioned that he knew about the validity of these issues from only some time back and not its present status. • Could you please help to confirm whether the issue(s) with the ss_* corner lib files still exist or are they resolved ? ◦ If they remain unresolved yet, is it sufficient to ensure that my design has some required minimum timing slack for the tt_025C_1v80 corner alone ? • Also, could you please explain/ point me to any documentation or discussion threads that explains the background of this issue ? EDIT: Adding the setup, hold slack plots across corners in comment below

share graphs here

Setup, Hold timing slack vs. PVT corner

@ArunKumar P.V Sorry, not my field of expertise.

No worries, thanks @Mitch Bailey Please feel free to tag anyone else you think might be able to help to this thread!

My go to person is @Tim Edwards, but he’s already tagged.

"the sky130 OpenPDKs being optimized only for the tt_* corners" is not a meaningful statement. Slow corners have issues because slow corners (slow-low-hot, specifically) are almost always the worst case and hardest to meet spec for.

@Tim Edwards, Thanks very much for your reply! Understood that it is not really an issue with the ss_low_voltage_* corner lib files, rather the actual behaviour of the silicon at this pvt corner. Yes, it is very difficult to close the timing at ss_low_volt corners as is evident from the plots. (Also, slow_cold seems slower than slow_hot for the same voltage) • Previously, I was checking timing closure only for the tt_* corners based on the guidance regarding the issue with ss_* lib files. • Now that you have clarified that there are no such lib-file related issues, is there a list of PVT corners that are mandatorily required to have timing closure if I want to tape-out a design using sky130_fd_sc_hd SCL for it to be accepted for an MPW shuttle (with the present real process variation spread observed) ? OR, • Is it up to the user to specify/ decide which all corners are needed to be closed w.r.t timing based on requirement/ specifications ? If it is the latter, I was thinking of skipping the ss_n40C_low_volt corners and use the next available slowest corner - which is ss_100C_1v40.

It is up to you to decide which corners you need to close timing on. Unless you intend to put this circuit into high-volume production, you can certainly get away with failures at slow-low-hot; I've done that plenty of times myself. I would not ignore the slow corner, but just try to minimize the failures.

@Tim Edwards do we have the RC table for other corners for extraction?

@Kunal: Yes, there are extraction style variants in magic for the R and C low and high corners.