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Hi <@U016EM8L91B> <@U017X0NM2E7> I am facing an is...
# analog-design
n
Hi @Tim Edwards @Mitch Bailey I am facing an issue with LVS. The cell nor_gate clears the LVS abut when it is a subcell of comp_driver, I am getting some property errors. The error has pin mismatch : *`VSS_DEL | VSUBS **Mismatch**`* . Can you please help me with the issue? I checked the substrate contacts but cant find any issue.
m
@naina singhal can you share your extraction and netgen commands?
n
@Mitch Bailey The extraction commands are : 
extract all , ext2spice lvs , ext2spice
 and the netgen command is : 
netgen -batch lvs "driver_xschem.spice driver" "comp_driver.spice comp_driver" /home/zerotoasic/asic_tools/pdk/sky130A/libs.tech/netgen/sky130A_setup.tcl
m
@naina singhal thanks. openlane runs lvs with the layout netlist first and the schematic netlist second, so it’s helpful to have the lvs command if your setup is different. The schematic netlist looks like a simulation netlist. Many of those parameters aren’t necessary for LVS. They shouldn’t cause a problem though. @Tim Edwards any ideas on the missing property error?
n
Ok Thank you @Mitch Bailey. I will change the required setup and netlist.
t
@Mitch Bailey: When I look at what triggers the property error, there is a 5v nFET, length 2, W=3 on one side, and 2x W=2 on the other side. I have no idea why the property error information is not being output, though. I will look into it when I have the time.
👍 1
n
Hi @Mitch Bailey @Tim Edwards Sorry to disturb you again. I am facing an LVS error during precheck. The LVS check in precheck is failing due to property errors but I can not find any issue. Moreover when I use 
user_analog_project_wrapper.gds.spice
 to run LVS locally, it passes. But it is failing during precheck. Can you please help me with the issue?
One more check that is failing is klayout FEOL. Can you please have a look at the log?
m
@naina singhal the netgen version on the platform precheck may need to be updated to catch the change that @Tim Edwards recently made to parameter calculations.
t
@naina singhal: What version of the mpw_precheck (i.e., git commit hash) produced that result?
n
@Tim Edwards How do I check the version?
Ok I will update the MPW precheck to the latest version @Tim Edwards @Mitch Bailey \
t
You may have the most recent version. I just want to know which version you are using so I can compare it to what is there now and see if there were any changes to the design rule deck for klayout.
n
I updated the mpw_precheck to version 
4efb33553ee6c2acdb0fa9a6a5f87af099f5c1d5
 but still have the same issue.
@Tim Edwards is this the recent version?
t
No, it's about 8 commits and a month behind the current version, but I didn't see any changes to the klayout decks since that commit.
n
I ran this version on one of my older design and it passed the precheck but again I did not use 20um length transistors in that design.
m
@naina singhal 1. can you share you drc results file? 
precheck_results/10_APR_2024___21_21_11/outputs/reports/klayout_feol_check.xml
2. ‘Moreover when I use 
user_analog_project_wrapper.gds.spice
 to run LVS locally’. What do you mean by run locally? Are you running a native netgen command? Do you include all the source netlists (if you don’t the ones that you don’t include are black-boxed (silently).
n
@Mitch Bailey Please see the attachment. For LVS I used the command 
netgen -batch lvs "user_analog_project_wrapper.spice user_analog_project_wrapper" "user_analog_project_wrapper.gds.spice user_analog_project_wrapper" /home/zerotoasic/asic_tools/pdk/sky130A/libs.tech/netgen/sky130A_setup.tcl
m
@naina singhal thanks! openlane lvs uses layout first, schematic second, so it’s good to include your command if you’re doing something different. For analog designs, the schematic spice file should be complete, however. Do you use any digital macros? Can you share 
precheck_results/10_APR_2024___21_21_11/tmp/lvs.report
?
n
Ok. I will use the layout netlist first from now on. I do not have any digital macros in my design. Please see the attachment.
m
@naina singhal both of your netlists are layout extracted netlists. Don’t you have a schematic generated netlist?
n
I have some pins it my cell which are not connected to anything in wrapper.
I think I found the issue with LVS. I was putting the wrong netlist (generated from layout) in the lvs folder. It was stupid ... sorry. Now LVS does fail but only because of the port errors. @Mitch Bailey Please see the latest lvs report. The port errors are there because there are some open pins in my cell. I put those pins to see voltages after pex simulations.
m
@naina singhal can you share your schematic generated spice netlist?
LVS is not comparing 
comp_0
Copy code
Circuit 2 cell comp_0 is a black box; will not flatten Circuit 1
n
@Mitch Bailey So sorry for confusions. Here are all the latest files : There is just one issue : There is one random metal1 pin in the layout created by mistake I guess. How to find it?
I remove all the unconnected pins and reconnect the cell to wrapper. Cell name is comparator_0 now.
m
io_analog[9:7
] seem to be connected differently. Layout
Copy code
Xcomparator_0_0 io_analog[10] vssa2 comparator_0_0/INN comparator_0_0/INP comparator_0_0/OUTPUT
+ io_analog[7] comparator_0

.subckt comparator_0 VDD VSS INN INP OUTPUT m1_1170_6492#
Schematic
Copy code
x1 io_analog[10] io_analog[7] io_analog[9] io_analog[8] vssa2 comparator_0

.subckt comparator_0 VDD OUTPUT INP INN VSS
Looks like 
io_analog[9:8]
are not connected in the layout. For the random pin, the database coordinates are in the net name - divide by 200. 
m1_1170_6492#
-> 5.85, 32.46
n
Ok @Mitch Bailey Thank you so much. I fixed all the wrong connections. So sorry for mistakes from my end. Now I am getting the same LVS errors I got before @Tim Edwards fixed them and updated the netgen : The PNP transistor property "m" mismatch error and dummy device merging issue. LVS is clean while running locally but failing during precheck, Here is the LVS report from latest precheck.
message has been deleted
@Mitch Bailey I cloned mpw_precheck from https://github.com/efabless/mpw_precheck.git for latest version. But the LVS issue is still there while running precheck.
m
Right, netgen in precheck needs to be updated.
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