Hello everyone. I tried top down optimization with user_project_example and user_project_wrapper. What I did is very simple. I wrote user_proj_example RTL in "VERILOG_FILES" in config json instead of user_proj_exmple Netlist, and I modified some parameter. But LVS error happened(many mismatches). Does someone know why this config.json doesn't work? 〇Updates in config.json "VERILOG_FILES": [ "dir::../../verilog/rtl/defines.v", "dir::../../verilog/rtl/user_project_wrapper.v", "dir::../../verilog/rtl/user_proj_example.v" ], "SYNTH_ELABORATE_ONLY": 0, 〇Removed from config.json "FP_PDN_MACRO_HOOKS": "mprj vccd1 vssd1 vccd1 vssd1", "MACRO_PLACEMENT_CFG": "dir::macro.cfg", "VERILOG_FILES_BLACKBOX": [ "dir::../../verilog/gl/user_proj_example.v" ], "EXTRA_LEFS": "dir::../../lef/user_proj_example.lef", "EXTRA_GDS_FILES": "dir::../../gds/user_proj_example.gds", "EXTRA_LIBS": "dir::../../lib/user_proj_example.lib", "EXTRA_SPEFS": [ "user_proj_example", "dir::../../spef/multicorner/user_proj_example.min.spef", "dir::../../spef/multicorner/user_proj_example.nom.spef", "dir::../../spef/multicorner/user_proj_example.max.spef" ], 〇LVS Error Circuit user_project_wrapper contains 409 device instances. Class: sky130_fd_sc_hd__a31o_2 instances: 12 Class: sky130_fd_sc_hd__a21o_2 instances: 10 Class: sky130_fd_sc_hd__dfxtp_2 instances: 33 Class: sky130_fd_sc_hd__buf_1 instances: 31 Class: sky130_fd_sc_hd__buf_2 instances: 31 Class: sky130_fd_sc_hd__nand4_2 instances: 1 Class: sky130_fd_sc_hd__a2bb2o_2 instances: 1 Class: sky130_fd_sc_hd__and3b_2 instances: 1 Class: sky130_fd_sc_hd__xor2_2 instances: 1 Class: sky130_fd_sc_hd__and4_2 instances: 3 Class: sky130_fd_sc_hd__inv_2 instances: 21 Class: sky130_fd_sc_hd__nand3_2 instances: 4 Class: sky130_fd_sc_hd__conb_1 instances: 175 Class: sky130_fd_sc_hd__and2b_2 instances: 1 Class: sky130_fd_sc_hd__and3_2 instances: 9 Class: sky130_fd_sc_hd__or2_2 instances: 4 Class: sky130_fd_sc_hd__nand2_2 instances: 9 Class: sky130_fd_sc_hd__mux2_2 instances: 17 Class: sky130_fd_sc_hd__and2_2 instances: 13 Class: sky130_fd_sc_hd__o211a_2 instances: 1 Class: sky130_fd_sc_hd__a221o_2 instances: 1 Class: sky130_fd_sc_hd__o2111a_2 instances: 1 Class: sky130_fd_sc_hd__a32o_2 instances: 17 Class: sky130_fd_sc_hd__a22o_2 instances: 1 Class: sky130_fd_sc_hd__o21a_2 instances: 7 Class: sky130_fd_sc_hd__and4b_2 instances: 1 Class: sky130_fd_sc_hd__o21ai_2 instances: 1 Class: sky130_fd_sc_hd__or2b_2 instances: 1 Class: sky130_fd_sc_hd__nor2_2 instances: 1 Circuit contains 645 nets, and 344 disconnected pins. Circuit 1 contains 409 devices, Circuit 2 contains 409 devices. Circuit 1 contains 1870 nets, Circuit 2 contains 645 nets. * MISMATCH *

@Yomei Harada look at the config.json file for

user_proj_example

for settings on how to use standard cell rows. If you look at the gds, you’ll probably see a bunch of empty spaces in your cell rows. In particular, you probably want to use

"PL_RESIZER_DESIGN_OPTIMIZATIONS": 1,
    "PL_RESIZER_TIMING_OPTIMIZATIONS": 1,
    "GLB_RESIZER_DESIGN_OPTIMIZATIONS": 1,
    "GLB_RESIZER_TIMING_OPTIMIZATIONS": 1,
    "PL_RESIZER_BUFFER_INPUT_PORTS": 1,
    "FP_PDN_ENABLE_RAILS": 1,
    "GRT_REPAIR_ANTENNAS": 1,
    "RUN_FILL_INSERTION": 1,
    "RUN_TAP_DECAP_INSERTION": 1,
...
    "RUN_CTS": 1,

and you probably don’t want

"PL_RANDOM_GLB_PLACEMENT": 1,

see https://armleo-openlane.readthedocs.io/en/latest/docs/source/configuration.html

Hi David. Thank you for your replay. After updated config.json as you said, openlane works as I hope. The root cause of this issue is that I used config.json for user_project_wapper without updating layout properties.