Hi, I'm planning to add wire bond/probe pads in the user area. Can anyone confirm the pad.drawing - 76/20 layer placed over metal 5 gives a glass cut, exposing metal 5? Is there any other layer to use or requirement to follow in exposing metal 5? there's a rule for pads: Min spacing of pad:dg to pad:dg - 1.270 um as well as a rule for M5: Min spacing between two met5 - 1.6 um. How close can a pad be to M5 metal that's not exposed?

Yes, I can confirm that layer 76:20 is glass cut. Make sure that metal5 extends beyond the glass cut by at least 2.7um. Other than that, the metal5 to metal5 spacing is all that you need to satisfy. Unless your pads need to be particularly small, I would recommend just using the cell layout

sky130_fd_io__pad_esd

from the I/O library.

Thank you for the response. I used the tools from: https://github.com/efabless/foss-asic-tools which don't have the io library. What is the recommended way to implement the esd pad? I see from a previous post there's no esd protection on such cell, but the

sky130_fd_io__top_gpiov2

cell provides such.

The

esd

in the name is meaningless. The cell contains just a pad, with metal5, glass cut, and a ring of metal4 contacted around the edge. The area under the pad is intentionally kept clear of metal4. There is nothing else in the cell.

Thank you for sharing this. A few questions. There's a ring of met5.short here, what is the purpose/effect of the .short layers? The design I'm working on involves supplying external currents and potentials, is there an esd protection circuit or some type of TVS diode I can implement? Thank you again.

The metal5 short ring is meant to preserve the net belonging to the pin as a separate net name. Usually I find it mildly irritating, because I have to have separate names for various power supply pins, but otherwise I just run with it.

This is much appreciated, thank you again for sharing.

Honestly, I have no idea. I was citing a rule that is part of a comprehensive rule deck but is not in the DRC manual. It might be a requirement specifically for bond pads; in other processes, I've seen rules for probe pads that were much less restrictive. Many foundry bond pad rules are for high yield in volume production.

Thank you for the response. With regard to the `test_io.gds`; I'm not sure on how to go about integrating this to my

netgen/user_analog_project_wrapper.spice

file to pass the LVS check. I'm attempting to use xschem to generate a symbol with two

sky130_fd_pr/lvsdiode.sym

and three ports for the IO pad, VSSIO, and VDDIO, which I'm inserting into the

user_analog_project_wrapper.sch

and generating a netlist with the

LVS netlist: Top level is a .subckt

option checked. I am just dropping the test_io.gds into the analog project wrapper without connecting anything at the moment. Thank you for your time.

Sorry, I didn't think about that fact that you'd probably want a netlist to go along with that layout. The netlist of the pad is short, so I'll just print it here:

*---------------------------------------------------------------------------
* sky130_ef_io__analog_minesd_pad_short:
*---------------------------------------------------------------------------
* Simple pad, straight through, with ESD diodes (1 each P and N).
* All busses except for VDDIO and VSSIO removed
*---------------------------------------------------------------------------

.subckt sky130_ef_io__analog_minesd_pad_short P_CORE VDDIO VSSIO P_PAD
R0 P_PAD P_CORE sky130_fd_pr__res_generic_m5 w=253 l=0.1

D0 VSSIO P_CORE sky130_fd_pr__diode_pw2nd_11v0 pj=1.02e+08 area=5e+13
D1 P_CORE VDDIO sky130_fd_pr__diode_pd2nw_11v0 pj=1.02e+08 area=5e+13
.ends

If you use the "combined" models, those diodes should be XD0 and XD1, since the continuous-binned diode models are only defined as subcircuits.

Thank you for sharing again, I appreciate the help. The

sky130_fd_pr__res_generic_m5

device doesn't get extracted from the layout, which results in a mismatch error. I've tried removing the device but am still having mismatch errors. I've attached a few of the outputs and extracted spice netlist as well as the

netgen/user_analog_project_wrapper.spice

. Thank you for any help here.