I have a macro that uses both vccd1 vdda1 .I am using "FP_PDN_MACRO_HOOKS": ["core_flat vdda1 vssa1 vdda1 vssa1", "core_flat vccd1 vssd1 vccd1 vssd1" ],.I also tried with "FP_PDN_MACRO_HOOKS": ["core_flat vdda1 vssa1 vdda1 vssa1"],In both cases ,vccd1 is causing mismathced during LVS check.Any suggestion is much appreciated Here are relevant files

@Md Omar Faruque Try this

"FP_PDN_MACRO_HOOKS": ["core_flat vdda1 vssa1 vdda1 vssa1,",
    "core_flat vccd1 vssd1 vccd1 vssd1"
    ],

@Mitch Bailey Thanks it worked. However, We have used mvn transistor for analog parts. But still gets an ERC check failed in precheck.

@Md Omar Faruque Looks like the soft check and CVC check are detecting problems. Can you share these files?

precheck_results/04_APR_2024___18_55_58/outputs/reports/soft.report
precheck_results/04_APR_2024___18_55_58/tmp/cvc.error.gz

soft.report,cvc.error.gz

@Md. Sajjad Hossain The soft connection report shows missing metal connections to vss for 3 level shifters and 3 DEMUX_final blocks. Can you check that these are connected to vss with metal (and not just through substrate).

Circuit 1: core_flat                                                              |Circuit 2: core_flat                                                              

---------------------------------------------------------------------------------------------------------------------------------------------------------------------
Net: vssd1                                                                        |Net: vssd1                                                                        
  sky130_fd_pr__res_generic_po/(end_a|end_b) = 6                                  |  sky130_fd_pr__res_generic_po/(end_a|end_b) = 6                                  
  sky130_fd_pr__nfet_01v8/(1|3) = 21                                              |                                                                                  
  sky130_fd_pr__nfet_g5v0d10v5/(1|3) = 12                                         |                                                                                  
                                                                                  |                                                                                  
(no matching net)                                                                 |Net: controller_layout_0.level_shifter_1.vssd1                                    
                                                                                  |  sky130_fd_pr__nfet_g5v0d10v5/(1|3) = 4                                          
                                                                                  |  sky130_fd_pr__nfet_01v8/(1|3) = 2                                               
                                                                                  |                                                                                  
(no matching net)                                                                 |Net: controller_layout_2.level_shifter_1.vssd1                                    
                                                                                  |  sky130_fd_pr__nfet_g5v0d10v5/(1|3) = 4                                          
                                                                                  |  sky130_fd_pr__nfet_01v8/(1|3) = 2                                               
                                                                                  |                                                                                  
(no matching net)                                                                 |Net: controller_layout_1.level_shifter_1.vssd1                                    
                                                                                  |  sky130_fd_pr__nfet_01v8/(1|3) = 2                                               
                                                                                  |  sky130_fd_pr__nfet_g5v0d10v5/(1|3) = 4                                          
                                                                                  |                                                                                  
(no matching net)                                                                 |Net: controller_layout_0.DEMUX_final_0.VSS                                        
                                                                                  |  sky130_fd_pr__nfet_01v8/(1|3) = 5                                               
                                                                                  |                                                                                  
(no matching net)                                                                 |Net: controller_layout_2.DEMUX_final_0.VSS                                        
                                                                                  |  sky130_fd_pr__nfet_01v8/(1|3) = 5                                               
                                                                                  |                                                                                  
(no matching net)                                                                 |Net: controller_layout_1.DEMUX_final_0.VSS                                        
                                                                                  |  sky130_fd_pr__nfet_01v8/(1|3) = 5

@Mitch Bailey analog_io[16:14] are 3.3V input signals....I have checked the layout . It looks like the connection got broken somehow while flattening the core.

It looks like the

analog_io[16:14]

signals have been buffered using 1.8V devices.

/Xmprj(user_proj_example)/Xinput1 for analog_io[14]
/Xmprj(user_proj_example)/Xinput2 for analog_io[15]
/Xmprj(user_proj_example)/Xinput3 for analog_io[16]

If these are actual analog signals, they probably shouldn’t be buffered. If they are 3.3V digital signals, you might consider using the

io_in_3v3

connection which includes ESD protection.

@Mitch Bailey .Analog_io pins are connected to 3 analog inputs that can vary the voltage from 0 to 5 V and we did not use any 1.8V buffers with analog_io[16:14]. We checked lvs for the blackboxed circuit outside the Openlane.It worked fine.Now I have couple of confusions. 1.We did not separate analog and digital ground. Could the ERC issue be because of it? .. 2.In wrapper analog_io are inout pins while I defined these pins as input pins in USER_PROJ_EXAMPLE according to blackboexd macro.IS it ok? 3.Only AIN1,AIN2 and AIN3 are connected to vdda1 and vssa1.All other pins are connected to vccd1 and vssd1.However we defined the blackboed module like this (* blackbox *) module core_flat( `ifdef USE_POWER_PINS inout vdda1, // User area 1 1.8V power inout vssa1, inout vccd1, inout vssd1, `endif input SEL1, input DIGITALIN1, input SEL3, input DIGITALIN3, inout SEL2, input DIGITALIN2, input AIN1, input AIN2, input AIN3 ); endmodule `default_nettype wire Is it correct?

@Md Omar Faruque openlane probably added buffers to

analog_io[16:14]

when you ran

make user_proj_example

. In the gate level verilog output

verilog/gl/user_proj_example.v

, check

Xinput1

,

Xinput2

, and

Xinput3

. I think there is a way to tell openlane to not buffer certain signals. Defining them as

inout

in the

core_flat

macro might work. 1. For LVS, you can add

isosubstrate

in magic around your analog macro to separate

vssa1

and

vssd1

. 2. This may be what allowed the buffers to be added. LVS shouldn’t be a problem, though. 3. If your

core_flat

module has

vccd1

and

vssd1

pins in the parent verilog and layout, this is correct.

2. Defining them in core_flat as inout was causing error before synthesis.Can I change analog_io to input instead of inout in user_project_wrapper? If so,what else I have to change in configuration?

@Md Omar Faruque Use

RSZ_DONT_TOUCH

to list nets or instances that should not be buffered.

@Mitch Bailey After using isosub for analog part,it is now failing LVS during hardening user_proj_exampe.It tells that no matching pin for vssa1. Though when I checked gds and magic file, vdda1 and vssa1 pins are created.Besides, I used "RSZ_DONT_TOUCH_LIST":["vdda1","vssa1","AIN1","AIN2","AIN3"], Could you please check it?

vccd1

is not connected to

core_flat

---------------------------------------------------------------------------------------
Net: vccd1                                 |Net: vccd1                                 
  sky130_fd_sc_hd__tapvpwrvgnd_1/VPWR = 1  |  sky130_fd_sc_hd__tapvpwrvgnd_1/VPWR = 1  
  sky130_fd_sc_hd__decap_6/VPB = 1         |  sky130_fd_sc_hd__decap_6/VPB = 1         
  sky130_fd_sc_hd__decap_6/VPWR = 1        |  sky130_fd_sc_hd__decap_6/VPWR = 1        
  sky130_ef_sc_hd__decap_12/VPB = 1        |  sky130_ef_sc_hd__decap_12/VPB = 1        
  sky130_ef_sc_hd__decap_12/VPWR = 1       |  sky130_ef_sc_hd__decap_12/VPWR = 1       
  sky130_fd_sc_hd__fill_1/VPB = 1          |  sky130_fd_sc_hd__fill_1/VPB = 1          
  sky130_fd_sc_hd__fill_1/VPWR = 1         |  sky130_fd_sc_hd__fill_1/VPWR = 1         
  sky130_fd_sc_hd__decap_8/VPB = 1         |  sky130_fd_sc_hd__decap_8/VPB = 1         
  sky130_fd_sc_hd__decap_8/VPWR = 1        |  sky130_fd_sc_hd__decap_8/VPWR = 1        
  sky130_fd_sc_hd__decap_3/VPB = 1         |  sky130_fd_sc_hd__decap_3/VPB = 1         
  sky130_fd_sc_hd__decap_3/VPWR = 1        |  sky130_fd_sc_hd__decap_3/VPWR = 1        
  sky130_fd_sc_hd__decap_4/VPB = 1         |  sky130_fd_sc_hd__decap_4/VPB = 1         
  sky130_fd_sc_hd__decap_4/VPWR = 1        |  sky130_fd_sc_hd__decap_4/VPWR = 1        
  sky130_fd_sc_hd__buf_4/VPB = 3           |  sky130_fd_sc_hd__buf_4/VPB = 3           
  sky130_fd_sc_hd__buf_4/VPWR = 3          |  sky130_fd_sc_hd__buf_4/VPWR = 3          
  sky130_fd_sc_hd__clkbuf_8/VPB = 2        |  sky130_fd_sc_hd__clkbuf_8/VPB = 2        
  sky130_fd_sc_hd__clkbuf_8/VPWR = 2       |  sky130_fd_sc_hd__clkbuf_8/VPWR = 2       
  sky130_fd_sc_hd__fill_2/VPB = 1          |  sky130_fd_sc_hd__fill_2/VPB = 1          
  sky130_fd_sc_hd__fill_2/VPWR = 1         |  sky130_fd_sc_hd__fill_2/VPWR = 1         
  sky130_fd_sc_hd__diode_2/VPB = 9         |  sky130_fd_sc_hd__diode_2/VPB = 9         
  sky130_fd_sc_hd__diode_2/VPWR = 9        |  sky130_fd_sc_hd__diode_2/VPWR = 9        
  sky130_fd_sc_hd__buf_2/VPB = 1           |  sky130_fd_sc_hd__buf_2/VPB = 1           
  sky130_fd_sc_hd__buf_2/VPWR = 1          |  sky130_fd_sc_hd__buf_2/VPWR = 1          
  sky130_fd_sc_hd__clkbuf_4/VPB = 1        |  sky130_fd_sc_hd__clkbuf_4/VPB = 1        
  sky130_fd_sc_hd__clkbuf_4/VPWR = 1       |  sky130_fd_sc_hd__clkbuf_4/VPWR = 1       
  sky130_fd_sc_hd__buf_8/VPB = 1           |  sky130_fd_sc_hd__buf_8/VPB = 1           
  sky130_fd_sc_hd__buf_8/VPWR = 1          |  sky130_fd_sc_hd__buf_8/VPWR = 1          
                                           |  core_flat/vccd1 = 1                      
                                           |                                           
Net: core_flat/vccd1                       |(no matching net)                          
  core_flat/vccd1 = 1                      |

@Mitch Bailey I am sorry,but i think files are mixed up.I uploaded some files after using isosub for analog parts .Besides,I used "RSZ_DONT_TOUCH_LIST":["vdda1","vssa1","AIN1","AIN2","AIN3"],Now I have issue during hardening user_project_example.It says vssa1 has no matching pin in 41-user_pro_example.lvs.lef.log.Let me upload the files here again

@Md Omar Faruque At the

user_proj_example

level, the

RSZ_DONT_TOUCH_LIST

is

analog_io1

,

analog_io2

, and

analog_io3

, right? Can you share

41-user_pro_example.lvs.lef.log

?

41-user_proj_example.lef.lvs.log

@Md Omar Faruque Can you share your

verilog/gl/user_proj_example.v

file?

@Mitch Bailey the left side of 41-user_proj_example.lvs.lef.log schematic or layout nets?Here is the file from gl/

Haven’t figured out what the problem is. However, I’d like to know why are you flattening the core layout? The lef file looks unnecessarily large. If you’re creating that with magic, you might try the

-hide

and

-pinonly

options.

@Mitch Bailey -hide for lef did not work.Later I tried flatten -dotoplables and it worked.However, still the same ERC error remains in prechekc failing LVS.I then tried deleting LVS_CONNECT_BY_LABEL" .this time the same error showed at hardening user_proj_example.I am sharing both files here again. Besides,I have another thought.While doing LVS in netgen outside the openlane ,it was failing as well.Later after ,we updated magic version and added these lines below. Updating version and adding these couple of lines in sky130b_setup.tcl made LVS passed. #--------------------------------------------------------------- # ReRAM #--------------------------------------------------------------- set devices {sky130_fd_pr__reram_reram_cell} foreach dev $devices { if {[lsearch $cells1 $dev] >= 0} { property "-circuit1 $dev" delete Tfilament_0 property "-circuit1 $dev" delete m area_ox } if {[lsearch $cells2 $dev] >= 0} { property "-circuit2 $dev" delete Tfilament_0 property "-circuit2 $dev" delete m area_ox } } The version was 8.3.464 while openlane uses 8.3.456. Should we try updating magic in Openalne?If so,how?I tried,though, redoing openlane setup ,but it looks like it installs by default 8.3.456.ANy suggestion is much apprictiable

@Md Omar Faruque The

cvc.error

is still showing analog signals input to buffers. Can you share your current

user_proj_example/config.json

file? For precheck LVS, you’ll need to add the spice file for

core_flat_v4

to the

LVS_SPICE_FILES

section of

lvs/user_analog_project_wrapper/lvs_config.json

.

yes,this is what confuses me a lot. Similarly there are some pins namely "vssa1eq0, vssa1uq1 .... in 41-user_proj_example.lvs.lef.log(while did not use LVS_CONNECT_BY_LABEL at user_proj_example) and in lvs.report for precheck (while used LVS_CONNECT_BY_LABEL). Yes,I used spice file from schematic for lvs_config.json

@Md Omar Faruque Can you share your current entire repo? I’m having trouble following the discussion.

@Mitch Bailey https://github.com/MdOmarFaruque/memristor_with_openlane/tree/main

There are 6 locations where metal1 is not connected to VSS in

core

.

@Mitch Bailey We used isosubstrate for the whole analog part.Is it ok or Shoud we use isosub for only pusbstrate of analog part?

@Md Omar Faruque The schematic

core

uses both

vssa1

and

vssd1

connections to substrate. The layout does not use

vssa1

. In order to make a layout that matches the schematic, connect the ground of the 3.3v/5.0v devices to

vssa1

and the vss of the 1.8v devices to

vssd1

. Then surround only the 3.3v/5.0v devices and their taps with

isosubstate

.

@Mitch Bailey I am sorry.I am a bit confused .You said "Then surround only the 3.3v/5.0v devices and their taps with

isosubstate

."By taps do you mean the power rings of vdda1 and vssa1?

Yes, the nwell and psubstrate connections.