@Mitch Bailey @Stefan Schippers hello i am trying to figure out to run post simulation but i am getting error in waveform which is unexpected could you please help me i have attached the files

@Rafeeq Khan Mohammed not sure if this is helpful or not, but it looks like you’re extracting the capacitances but not the resistances. Is that your intention? What you might try is create a simulation file that `.include`s the schematic generated netlist instead of appending the netlist to the end of the file. Then, when you want to simulate the extracted netlist, you just change the include file. You need to be sure that the pins are in the same order though. You can do this using

read spice

in magic before extracting or by making a wrapper cell like this.

.subckt core DigitalIN1 AIN1 SEL1 DigitalIN2 AIN2 SEL2 DigitalIN3 AIN3 SEL3 VSS VD VDD
Xcore_layout VDD VD VSS AIN1 DigitalIN1 SEL1 AIN3 SEL3 DigitalIN3 AIN2 DigitalIN2 core_layout
.ends

@Mitch Bailey thank you This first time I was trying to figure out for post simulation I was following some tutorial Maybe I will try extracting the resistance Also What I did is that created a symbol of whole circuit and made it as test bench in the spice object I included the layout extracted spice file If the pins have order change how do I make correct by manually in spice file I should change ?

To get the correct pin order in the extracted netlist, use

readspice <spicefile>

. You can read about it here. If you want to use a extracted netlist with pins in a different order, I suggest you create a wrapper cell as explained above. The only purpose is to change the order of the connections.

@Mitch Baileythank you for the info i tried to use that command but its failing

You have spaces in your filename. try

readspice "filename"

or

readspice {filename}

@Mitch Bailey thank you but i am getting this as could not be loaded

looks good! you just want the port orders annotated. Be sure that the layout cell name matches the netlist name

core

. (not

core_layout

).

@Mitch Bailey Do I need to have the all cells names same in schematic and layout for post simulation as only top level cleared and other its showing as unknown subckt error

@Rafeeq Khan Mohammed

Do I need to have the all cells names same in schematic and layout for post simulation

Your layout should be flattened so only the top cell matters. Not aware of any version dependencies.

@Mitch Bailey okay thank you and could you please say about this issue why it's happening how do I get the port orders extract from the file where readspice has been done

@Tim Edwards (sorry)

@Tim Edwards.

@Rafeeq Khan Mohammed: What you did up above---"_I tried to change the names of all the cells but after modifying the ports, the last subfile is opening as a "not gate" after doing read spice_" looked correct. Because it was a hierarchical layout, each cell was loaded in turn and annotated. After that you should have returned to the top level with

load <top_cell>

and then done

writeall

. Then extracting the top level should generate a netlist with the corrected port order.

@Tim Edwards okay thank you I will try now