Hi all, I have a doubt regarding caravel RTL simulation, I have two GPIO inputs both defined as GPIO_MODE_USER_STD_INPUT_NOPULL in the C file, both are configured with the same signal in the testbench verilog but when I see the simulation one signal has a X value instead of 0 and the other one works correctly. Attached is the simulation showing this behavior. What could cause this behavior, is it due to the use of GPIO 36?

@Emilio Baungarten you’re simulating

caravel

not

caravan

, correct? If these signals are both inputs, I expect that the testbench is driving them. What testbench are you using?

I started with the

io_ports

example and modified some things to simulate my module, I attach the verilog file. on line 320 I have

assign mprj_io[36] = prog_clk[0];

, on line 327 I assign _gfpga_pad_GPIO_PAD[0]_ to _mprj_io[26]_ (

assign {mprj_io[24],mprj_io[25],mprj_io[26]} = gfpga_pad_GPIO_PAD[2:0];

) and then on line 343 I assign _prog_clk[0]_ to _gfpga_pad_GPIO_PAD[0]_ (

assign gfpga_pad_GPIO_PAD[0] = prog_clk[0];

).