Hi, I'm currently in the process of porting Caravel with VexRiscV mindebug specs onto an FPGA for testing purposes and the simulation runs correctly, but when I upload the bitstream onto the actual FPGA board nothing runs. I believe narrowed the issue down to mgmtsoc_litespidrphycore_clk since the flash_clk for flash_spi programming is connected to the mgmtsoc_litespidrphycore_clk. I'm not exactly sure what's going on since in the simulations it shows that the mgmtsoc_litespidrphycore_clk is running correctly but when I track the flash_clk/mgmtsoc_litespidrphycore_clk using a basic counter to blink an LED it fails/the clock is not running.

Did you use LiteX to generate the rtl or are you using a custom design ?

LiteX to generate

Can you provide your target and platform script ? Which fpga are you using ?

I am using the ZedBoard FPGA and where can I find the target/platform script?

you can find the target and platform script for your board at litex/litex_boards . Here you can see a tutorial i wrote for litex. Some Zynq devices have problem with uart pin constraints in LiteX. Please feel free to ask any question you have 🙂