Aadhithya koramoni
04/01/2024, 7:30 PMMitch Bailey
04/01/2024, 11:51 PMBR_EN
is being driven in 2 blocks on the posedge of CLK
. The block starting at line 80 and the block starting at 211. This one of the errors.Aadhithya koramoni
04/02/2024, 12:35 AMMitch Bailey
04/02/2024, 12:47 AM1-synthesis_pre_synth.chk.rpt
shows at least 2 errors in addition to all the warnings. The errors are what is stopping openlane. You might be able to proceed to PnR, but your design might not work because you have multiple drivers for the same net. (It is conceivable that if the inputs to the drivers were always the same logical level, that there might not be a problem.)Aadhithya koramoni
04/02/2024, 1:30 AMMitch Bailey
04/02/2024, 2:47 AM"QUIT_ON_SYTHN_CHECKS": 0,
Diana Natali Maldonado Ramirez
04/02/2024, 3:45 PMAadhithya koramoni
04/02/2024, 5:23 PM