Hi everybody, I would like to know how could I add a digital part to user_analog_project_wrapper? I mean, to obtain a similar result as when in caravel I do make user_proj_example and then make user_project_wrapper. I copied the openlane from caravel to caravan, I changed the pin_order.cfg so they could be similar to user_project_wrapper_empty (but I don’t know if this is correct) and I also tried to add from Magic, but it was not possible to open two different .gds files, this is, the user_project_wrapper_empty and the user_proj_example.gds. I also tried with Klayout and I also could not integrate both .gds. Could you please help me with an explanation about how this should be done? Thanks in advance!

@JONATHAN ARMANDO PATIÑO

user_project_wrapper

and

user_analog_project_wrapper

have different ports. Can you find a

user_analog_project_wrapper_empty.gds

file that contains the ports? You should be able to run

make user_analog_project_wrapper

, but there may still be a problem with

caravel_user_project_analog/openlane/Makefile

. It should be the same as

caravel_user_project/openlane/Makefile

. If it isn’t, I think you can just copy it. If your analog blocks are hard macros, you can use openlane to route them just like digital blocks. You may want to edit the wires manually afterwards because openlane generally routes with (close to) minimum width wires.

@Mitch Bailey Yes, I found user_analog_project_wrapper_empty.gds at https://github.com/efabless/caravel/tree/main/gds, then I observed it with KLayout and configured the pin_order.cfg for user_project_example and pin_order.cfg for user_analog_project_wrapper. After that, I executed 'make user_project_example' and 'make user_analog_project_wrapper'. I encountered an error. Attached are the error message and the config.json files.

@JONATHAN ARMANDO PATIÑO I don’t think

pin_order.cfg

is needed for

user_analog_project_wrapper

(or

user_project_wrapper

). The pin positions come from the def file. There should be something like

"FP_DEF_TEMPLATE": "dir::fixed_dont_change/user_project_wrapper.def",

but with the analog version. Looks like it’s available in the caravel repo in the def directory.

@Mitch Bailey Thanks for your answer! I replaced the file user_project_wrapper.def by user_analog_project_wrapper.def. There is also a file named user_project_wrapper_gf180mcu.def but I couldn’t find its analog version (although I don’t know if it’s necessary), then I did make and I got the next error, but I don’t understand why or what is producing it:

/logs/floorplan/4-apply_def_template.log"

[ERROR]: Exit code: 1

[ERROR]: Last 10 lines:

Wrote pin wbs_sel_i[3] at layer met2 at (126729, -4000, 127289, 2400)...

[ERROR]: Pin wbs_sel_i[3]'s coordinate 126729 does not lie on the manufacturing grid.

[ERROR]: Pin wbs_sel_i[3]'s coordinate 127289 does not lie on the manufacturing grid.

Wrote pin wbs_stb_i at layer met2 at (26259, -4000, 26819, 2400)...

[ERROR]: Pin wbs_stb_i's coordinate 26259 does not lie on the manufacturing grid.

[ERROR]: Pin wbs_stb_i's coordinate 26819 does not lie on the manufacturing grid.

Wrote pin wbs_we_i at layer met2 at (32169, -4000, 32729, 2400)...

[ERROR]: Pin wbs_we_i's coordinate 32169 does not lie on the manufacturing grid.

[ERROR]: Pin wbs_we_i's coordinate 32729 does not lie on the manufacturing grid.

child process exited abnormally

[ERROR]: Step 4 (floorplan) failed with error:

-code 1 -level 0 -errorcode NONE -errorinfo {

while executing

"throw_error"

(procedure "try_exec" line 17)

invoked from within

"try_exec $::env(OPENROAD_BIN) -exit -no_init -python {*}$args  --input-lef $::env(MERGED_LEF)  --output-def $arg_values(-output_def)  --output $arg_va..."

(procedure "manipulate_layout" line 19)

invoked from within

"manipulate_layout $::env(SCRIPTS_DIR)/odbpy/apply_def_template.py -indexed_log $log -output_def $::env(CURRENT_DEF) --def-template $::env(FP_DEF_TEMPL..."

(procedure "apply_def_template" line 7)

invoked from within

"apply_def_template"

(procedure "run_floorplan" line 38)

invoked from within

"run_floorplan"} -errorline 1

@JONATHAN ARMANDO PATIÑO looks like the

user_analog_project_wrapper.def

file in the repo has several hundred pins that are a little off. The def file is supposed to ensure that the ports match to the caravel framework. I made a patch that should allow you to run openlane. Can you download and try this file? If it passes openlane and precheck, I create a pull request. Thanks for reporting the problem.

@Mitch Bailey Hi, thanks for your answer. Now I used the new user_analog_project_wrapper.def and openlane ran until the next Step: (attached the error) Thanks!

[STEP 29]

[INFO]: Running LVS (log: ../home/jona/Desktop/prueba_project/prueba_caravan_openlane/caravel_user_project_analog/openlane/user_analog_project_wrapper/runs/24_03_27_12_01/logs/signoff/29-lvs.lef.log)...

[ERROR]: There are LVS errors in the design: See '../home/jona/Desktop/prueba_project/prueba_caravan_openlane/caravel_user_project_analog/openlane/user_analog_project_wrapper/runs/24_03_27_12_01/reports/signoff/29-user_analog_project_wrapper.lvs.rpt' for a summary and '../home/jona/Desktop/prueba_project/prueba_caravan_openlane/caravel_user_project_analog/openlane/user_analog_project_wrapper/runs/24_03_27_12_01/logs/signoff/29-lvs.lef.log' for details.

[ERROR]: Step 29 (lvs) failed with error:

-code 1 -level 0 -errorcode NONE -errorinfo {

while executing

"throw_error"

(procedure "quit_on_lvs_error" line 13)

invoked from within

"quit_on_lvs_error -rpt $count_lvs_rpt -log $log"

(procedure "run_lvs" line 76)

invoked from within

"run_lvs"

(procedure "run_lvs_step" line 10)

invoked from within

"run_lvs_step"} -errorline 1

[INFO]: Saving current set of views in '../home/jona/Desktop/prueba_project/prueba_caravan_openlane/caravel_user_project_analog/openlane/user_analog_project_wrapper/runs/24_03_27_12_01/results/final'...

[INFO]: Generating final set of reports...

[INFO]: Created manufacturability report at '../home/jona/Desktop/prueba_project/prueba_caravan_openlane/caravel_user_project_analog/openlane/user_analog_project_wrapper/runs/24_03_27_12_01/reports/manufacturability.rpt'.

[INFO]: Created metrics report at '../home/jona/Desktop/prueba_project/prueba_caravan_openlane/caravel_user_project_analog/openlane/user_analog_project_wrapper/runs/24_03_27_12_01/reports/metrics.csv'.

[INFO]: Saving runtime environment...

[ERROR]: Flow failed.

[INFO]: The failure may have been because of the following warnings:

[WARNING]: Module sky130_ef_sc_hd__decap_12 blackboxed during sta

[WARNING]: Module sky130_fd_sc_hd__fill_2 blackboxed during sta

[WARNING]: Module sky130_fd_sc_hd__fill_1 blackboxed during sta

[WARNING]: Module sky130_fd_sc_hd__tapvpwrvgnd_1 blackboxed during sta

[WARNING]: VSRC_LOC_FILES is not defined. The IR drop analysis will run, but the values may be inaccurate.

@JONATHAN ARMANDO PATIÑO Sorry, missed your post. Showing LVS errors now. Can you share

logs/signoff/29-lvs.lef.log

and

reports/signoff/29-user_analog_project_wrapper.lvs.rpt

?

Hi, don't worry. The

logs/signoff/29-lvs.lef.log

is the one above, but it's attached here again, and I also attached the

reports/signoff/29-user_analog_project_wrapper.lvs.rpt

:

Can you share

logs/signoff/29-user_analog_project_wrapper.lef.lvs.log

, too? Incidentally, your netgen may be a little old. I’m currently using

1.5.272

- you have

1.5.255

. There were some changes dealing with shorted top level pins.

Sure! Here's the requested log: logs/signoff/29-user_analog_project_wrapper.lef.lvs.log.

@JONATHAN ARMANDO PATIÑO looks like your layout for

user_proj_example

is using

io_in[24:14]

etc. while the verilog has

io_in[10:0]

etc.

@Mitch Bailey Thank you so much, I fixed the problem with the pins and now I ran make run-precheck and got the next error:

@JONATHAN ARMANDO PATIÑO

Default

just means you need to change your

README.md

file so that it’s more than 75% different than the default.

Consistency

is a strange check for analog designs. I think you can eliminate it my copying the extracted netlist

precheck_results/28_MAR_2024___23_23_11/tmp/ext/user_analog_project_wrapper.gds.spice

or

precheck_results/28_MAR_2024___23_23_11/tmp/spice_fix/user_analog_project_wrapper.spice

to

netgen/user_analog_project_wrapper.spice

.

XOR

is a problem and may be due to the adjusted def file. You can open the result gds file

precheck_results/28_MAR_2024___23_23_11/outputs/user_analog_project_wrapper.xor.gds

in klayout (or there shoulld be an xml marker database) and see where the layers mismatch. If it is caused by the pin adjustments, it might be easier to open the layout in klayout, make sure the wires line up with the pins (don’t move the pins) and save the gds. You probably shouldn’t do this in magic.

LVS

probably needs more information. Can you share

precheck_results/28_MAR_2024___23_23_11/tmp/lvs.report

? One thing you’ll most certainly need is the gate level verilog generated for

user_proj_example

. Be sure to add that to the

lvs/user_project_wrapper/lvs_config.json

file in the

LVS_VERILOG_FILES

section.

@Mitch Bailey Ok. Here is lvs.report.

The default

lvs/user_analog_project_wrapper/lvs_config.json

file uses a top level netlist created from xschem and located in

xschem/user_analog_project_wrapper.spice

. How did you run openlane on

user_analog_project_wrapper

or did you manually integrate

user_proj_example

? If you ran openlane, then you can just add

verilog/gl/user_proj_example.v

and

verilog/gl/user_project_wrapper.v

in the

LVS_VERILOG_FILES

section of

lvs/user_analog_project_wrapper/lvs_config.json

. If you manually integrated, you can use xschem to place a symbol for

user_proj_example

in the

user_analog_project_wrapper

schematic and connect it along with any other cells at the top level.

So far, as an example what I did first was to add the https://github.com/efabless/timer-tutorial in rtl caravan, then with run openlane. The final idea is to be able to integrate the two stages in the analog design manually and the digital part with openlane. How would that be possible?

So if I understand you correctly, you ran openlane on

user_analog_project_wrapper

and then want to manually add analog blocks and change the wiring later? Or did you run openlane on

user_proj_example

and plan to do the top

user_analog_project_wrapper

all by hand?

Yes, I'm planning to do the first option, first run openlane and then the wiring with an analog block, since the idea is to take measurements from an analog block and analyze them in the risc-V

hmm. blazing into new territory. Since you have the gate level

user_analog_project_wrapper

verilog output from openlane, my suggestion is to 1. copy

verilog/gl/user_analog_project_wrapper.v

to something like

verllog/gl/user_analog_project_wrapper+macro.v

. 2. create the spice for the analog blocks that you want to add from xschem. 3. add the connections to these blocks manually in

user_analog_project_wrapper+macro.v

but don’t create verilog stubs. 4. in your

lvs_config.json

file, add the analog spice files to the

LVS_SPICE_FILES

and the verilog files (

user_proj_example.v

and

user_analog_project_wrapper+macro.v

) to

LVS_VERILOG_FILES

. 5. let me know if it works 😬

Hi @Mitch Bailey. I continue working with this but I need to add a macro in user_analog_project_wrapper, I mean, I have a digital macro (which I’ve already added with openlane) - user_analog_proj_example - but then I can not add the analog design with openlane. Should I extract with magic the .lef and .gds and then add them to openlane? So far I’m trying with a simple inverter designed by Magic, due to the example_por (caravan example) throws an error when I extract the gds in magic. Maybe you have an example or a clear idea about how to add it? Thanks!

@JONATHAN ARMANDO PATIÑO Anytime you want to place a hard macro with openlane you will need a lef file and a gds file. You can create both of these from magic. I recommend using

-hide

and

-pinonly

with your

lef write

command if your macro is large.