Hello, I have a question. Is Nwell not required when drawing a PFET inside Deep Nwell? Klayout Pcell did not generate Nwell, but design rules define Min. DNWELL enclose Nwell.

The GF design rules are more than a little ambiguous on this point, as it is not clear what you get inside a DNWELL region that has neither NWELL nor PWELL drawn. I would strongly suggest drawing NWELL underneath the device.

https://mithro-gf180mcu-pdk.readthedocs.io/en/latest/physical_verification/design_manual/drm_04_4.html this is the truth table for the devices that is the reference to detect devices for LVS: all pFETs have NWell=1 ("1" is "required", "0" is "forbidden", "X" is "don't care")