Process question: With a 5 V supply, can I use standard 1.8V PMOS transistors from the positive supply, provided I put the transistors in a deep nwell, and make sure that none of the transistor connections deviate more than 2.1 V (or whatever the absolute maximum rating is) from the positive supply?

@Christoph Maier I don’t think deep nwell will do anything for pmos transistors. You could put the nmos transistors over deep nwell and connect the pwell and nmos source to 3.2V. The thin-oxide cmos logic would then operate in the 3.2V-5V range instead of the usual 0V-1.8V range. Be careful with external inputs though - 0V input would break things.

@Mitch Bailey, that's the general idea … native pmos (even over deep well) might match better than 5V transistors … but the lengths to which I'd need to go to protect the pmos thin oxide gates may be defeating the advantage.

@Christoph Maier I wouldn’t consider myself a seasoned circuit designer. However, for the past 20+ years, I’ve been doing full chip reliability checks, so I am a seasoned circuit checker. My knowledge isn’t specific to the sky130 process; I work with leading edge processes too.

@Mitch Bailey, thanks, that helps! The gotcha with open forums is that now you need to do reliability checks on all the answers that you get to a question. Now I "only" need to get information about high voltage device layout (how much bigger are 5V transistors than 1.8V transistors on top of a deep well?) in order to make the correct design decisions for the schematic review. The days when, once you were in the walled garden of IC design, you would have one authoritative physical design rule document, seem to be over.