Hi, When extracting clean netlists from some layouts, there's no

subckt

for the top module, or it may have a different name. Is there a way to force the

subckt

definition, and with a specific device name?

A subcircuit will have the same name as the cell in magic. To ensure that it outputs as a subcircuit, then the cell must define

ports

(which appear as blue labels, instead of the default yellow for non-port labels). The

port

labels define the pins of the subcircuit, and the port indexes define the pin order.

I haven't mentioned that the layout was made with Klayout. I'm not sure if it has a

port

concept different than the layers that start with

label

. The thing is that I'm trying to do lvs on a Padframe, so I would like to avoid manual addition of ports in the top cell. There's a way to reuse some of the ports defined on the hierarchy? This padframe is composed with a klayout script that creates hierarchies with the pads, but none of those intermediate cells have ports defined. Is that a problem? Adding VDD, VSS DVDD and DVSS on top cell doesn't generates the

PADRING_DEFAULT_SPACING

subckt, only the

default_spacing

without ports. Should I have to put the ports on all the hierarchy?

@aquiles viza magic works well when there are ports (labels and pins) on all hierarchies. klayout should have a pin layer in addition to the label layer. This allows a differentiation between labeled nets and actual ports (at the top level). One solution in klayout may be to programmatically flatten cells with no pins before gds export. I haven’t worked out a solution to programmatically flatten intermediate hierarchies in magic yet.

When you said "flatten cells with no pins", you mean somethink like put the content of a cell in her parent, but maintain the lower cells, right? My Hierarchy is

PADRING_DEFAULT_SPACING:
   default_spacing:
        gf180mcu_fd_io__fill10
        gf180mcu_fd_io__fill5

If I understood correctly, I'm thinking that this could be possible

PADRING_DEFAULT_SPACING:
   gf180mcu_fd_io__fill10
   gf180mcu_fd_io__fill5

The netlist extraction was mantaining

default_spacing

, but ignores

PADRING_DEFAULT_SPACING

. If I "flatten" that cell into the top one, maybe I will get the subckt I'm expecting.

As @Tim Edwards says, unless you have ports (not just labels) at the top level, I don’t think a subcircuit will be extracted.