Hi, I'm working with @Gabriel Maranhão to do LVS on our padframes, but we are unable to do it on individual pads. Gabriel is using klayout gui and I am using klayout and magic/netgen with scripts, but neither of us have managed to get lvs clean. Has anyone gotten a clean lvs on the pads?

Maybe @Ashbir Aviat Fadila can give some hints?

@aquiles viza Looks like a couple of the diodes are not being extracted correctly.

.subckt np_6p0_CDNS_406619531451 MINUS
D0 VSUBS MINUS diode_nd2ps_06v0 pj=82u area=40p
.ends

.subckt pn_6p0_CDNS_4066195314552 w_n120_n120# PLUS
D0 PLUS w_n120_n120# diode_pd2nw_06v0 pj=0.106m area=0.15n
.ends

.subckt np_6p0_CDNS_4066195314553 MINUS
D0 VSUBS MINUS diode_nd2ps_06v0 pj=0.106m area=0.15n
.ends

np_6p0_CDNS_406619531451

and

np_6p0_CDNS_4066195314553

are extracted with only 1 terminal. Try `flatglob`ing the diodes before extracting. Klayout is extracting the mos capacitor as a

C

device instead of the expected

X

device. netgen will work with the netlists in either order, but openlane is setup to use the layout extracted netlist first and the source netlist second.

It worked, thanks David. I will perform lvs on all pads, if something happens I will ask for help

@aquiles viza nice work.

flatglob

only works on leaf cells - cells with no subcells. If cells with unflattened subcells are `flatglob`ed, you may get strange results. You can check the extracted netlists to see which subcircuits are being extracted. I recommend flattening subcircuits that have no explicit ports. In the extracted netlists, these are the subcircuits that only have hierarchical nets as ports (contain

/

) or automatically generated node names (contain

#

).

@aquiles viza: This script works for me to run LVS on the

bi_t

I/O cell:

Hi @Tim Edwards, I've modified the routine that loads the GDS, adding the reading of a LEF file and a spice extracted from xschem. Now the LVS works for almost all the devices.

# asig_5p0  Final result: Circuits match uniquely.
# cor       Final result: Circuits match uniquely.
# dvdd      Final result: Circuits match uniquely.
# dvss      Final result: Circuits match uniquely.
# fill5     Final result: Circuits match uniquely.
# fill10    Final result: Circuits match uniquely.
# bi_24t    Final result: Circuits match uniquely. Property errors were found.
# bi_t      Final result: Circuits match uniquely. Property errors were found.
# in_c      Final result: Circuits match uniquely. Property errors were found.
# in_s      Final result: Circuits match uniquely. Property errors were found.
# brk2      Final result: Verify:  cell has no elements and/or nodes.  Not checked.
# brk5      Final result: Verify:  cell has no elements and/or nodes.  Not checked.
# fill1     Final result: Verify:  cell has no elements and/or nodes.  Not checked.
# fillnc    Final result: Verify:  cell has no elements and/or nodes.  Not checked.

The problems you mentioned on the last comment can be solved by simply specifying the LEF file and a spice as reference for the port order? The attached files contains the reports and extracted netlists for pads with property errors

@aquiles viza Nice work! Can you share your lvs script? There seem to be some irrelevant parameters on the devices. The setup file should remove those.