https://open-source-silicon.dev logo
Join Slack
Powered by
I'm working on a relaxation oscillator which has j...
# analog-design
m
I'm working on a relaxation oscillator which has just started oscillating after a lot of time fiddling!
✅ 1
Any suggestions for getting a larger oscillation amplitude?
Also, I'm hitting a general issue with ngspice convergence - for example if I decrease the resistors from 22k to 11k ngspice goes from 10seconds sim time to 'so long I kill the process'
Why does that happen and any tips on dealing with it?
This design in general seems very sensitive to convergence, like changing the timestep, the current sources, any small thing will stop it oscillating or not converge
maybe I'm still missing something fundamental
c
@Matt Venn, could it be that this particular topology is a back-to-back inverter flip-flop that isn't supposed to oscillate?
m
it could be
I'm just copying the circuit from something i found online
c
Looks like the schematic you drew could be used as latch in a comparator, and you're exploring the pitfall of comparator metastability …
😅 1
Hmm. I'd need an exemption from the schematic-level CACE adherence design review on Friday to spend (fun, in comparison) time on this. I wouldn't use resistors in such a schematic. They're expensive, anyhow. Capacitors would be cheaper.
m
right now I'm not concerned with the circuit elements, just trying to get it to oscillate!
pretty sure my graph above was just some glitch in ngspice
m
I’m not an expert on analog circuits, but it seems to me that the capacitor is connected to ground on both sides (unless there’s some large resistance in the ammeter). Maybe the double circles with the 
V
is not an ammeter.
c
Hmmm … under what circumstances could I get such a thingy on actual silicon, hors compétition, https://fediscience.org/@christophmaier/110852885969761229 with only the in-house standards of scientific excellence being considered Competent Jurisdiction? https://fediscience.org/@christophmaier/110855315328266928 "Creativity is combining facts no one else has connected before"
As for back-to-back CMOS inverters wired up in a circlejerk [is this the correct technical term?] as oscillator, the general design rule is: Then shalt thou count to three, no more, no less. Three shall be the number thou shalt count, and the number of the counting shall be three. Four shalt thou not count, neither count thou two, excepting that thou then proceed to three. Oddly enough, Five is right out. doesn't apply. Five inverters in a circle jerk would also work.
m
@Christoph Maier I don’t think these are inverters. For inverters, the mosfets with connected gates also have connected drains, right?
m
The circle things are current sources
c
@Mitch Bailey, indeed the pmos transistors are nonlinear parallel resistors to the linear high resistive poly resistors. Strange.
Ah, now I get where the capacitor that I was missing has ended up. The "ammeters" are ideal current sources (which make SPICE convergence notoriously sketchy), and the capacitive coupling between the stages of the astable multivibrator that I was missing is through the (for small-signal purposes) floating sources of M1 and M2.
m
@Matt Venn Once again, my ignorance shines through. I don’t have experience simulating current sources, but I assume that in this instance, rather than an external input, the current sources represent the abstraction of an actual on chip circuit. I wonder if replacing the abstraction with an actual current source circuit would make a difference.
✅ 1
c
It would. Ridiculously long nmos transistors as current sources would be 1. something you could actually implement on silicon 2. a circuit element that SPICE is actually designed and optimized to handle — unlike ideal current sources
✅ 1
m
yes that's right David
so I can draw less stuff and concentrate on the oscillator bit
I don't even know how to size a transistor to use as a current source, and I don't even know what order of magnitude I need. I guess high is a safe bet
c
I've been AWFULLY distracted with tool chain installation and configuration inconsistencies, in particular the CACE moving target, but the cell I've actually promised to deliver are current sources, so as soon as I have done the necessary $stuff to pass chipalooza 2024 schematic design review end of the week, I'll write characterization schematics for exactly that problem [something along the lines of https://github.com/tatzelbrumm/teachingskilldemo/blob/master/TransistorCharacterization.pdf], ideally so that I can adapt to all sorts of other people's requirements. (as opposed to CACE syntax compliance)
🙌 1
✅ 1
m
@Mitch Bailey your idea was totally correct
✅ 1
message has been deleted
💡 1
👍 1
wrong nets (should have labelled them)
message has been deleted
👍 1
now tuned to 2MHz. frequency is 1 / RC
why did the current sources not work?
I don't even need to set initial conditions
c
SPICE doesn't like high impedance or floating nodes.
m
In simulation, probably won’t make much difference, but in the actual layout, you probably want to use one transistor/resistor pair to drive both M6 and M8 with the same signal.
✅ 1
c
Except that you want to avoid using resistors on silicon altogether as a matter of general principle, if you can help it. As for the "wrong" nets, these may be very instructive to see how the oscillator actually works. Are these the nmos transistor sources connected by C1?
m
not sure, I'd have to go back to that commit and read the spice
c
Label all the nets, and plot both source and drain voltages of your main nmos transistors. And save a transistor and a resistor as recommended by @Mitch Bailey while you're at it.
m
message has been deleted
message has been deleted
so I think it was each side of the cap before
yep
t
@Matt Venn: If you want complete full swing, you will need to pass the output to a regular inverter. The cross-coupled pMOS design will not get down to zero volts because the lowest voltage still needs to maintain a threshold voltage drop on Vgs of the two nFET devices, plus some non-zero drop across the two current source nFETs.
✅ 1
m
just trying to do that now
some reason standard cells aren't simulating
c
Then draw the inverter by hand.
m
no, I've already drawn enough inverters by hand!
c
If the tool chain idiosyncrasies are the choke point, drawing transistors is faster …
m
I'm learning to teach, so my aims are different
✅ 1
c
Not so different, maybe … anyhow, as long as you can put the source and drain voltages, and the inverter outputs into one graph, and maybe the branch currents in a second graph with time scales aligned, that will be most instructive, in my more or less humble opinion.
m
@Matt Venn With the lowest output voltage at 0.5V, the inverter pmos may never be in an off state. You might consider using a level shifter instead of an inverter to get the full swing (which you’d need to design yourself). Are you creating an adjustable oscillator? By varying the current through the current mirror, you can control the frequency, right?
m
I'm really at the early stages here, I'm just elated to see it oscillate after about 10 hours of work
👍 3
I've just added an inverter on the output to get full swing
I had to power it up correctly, that's what wasn't working before
message has been deleted
✅ 1
message has been deleted
good point to leave it for now
🌄 1
thanks for the help all!
c
One more thing … try hooking up the inverter to osc_b instead of nfet_drain. Won't unbalance the oscillator nearly as badly, I guess.
m
ah yes, totally forgot to set that back when I was messing about with the inverter
message has been deleted
much better
m
I wonder if a level shifter would give a squarer wave.
m
so much to learn
✅ 1
I want to learn how to buffer a node, so I could take osc_a and put it on an analog pin without loading the node
c
First of all, you want to develop an intuition for high-impedance vs. low-impedance nodes in a circuit. You want to monitor the high-impedance nodes in simulation (so by sheer accident, your wrong nodes in the first graph were the ones providing most insight), but for loading your building block with other circuitry, you want to use the low-impedance nodes. You also want to be able to monitor the currents in your different branches from Vdd to Vss. A big inverter as buffer will produce a nice, square output voltage, but at the possible expense of transient current spikes. This is particularly important for level shifters.
✅ 1
t
@Mitch Bailey: "_I wonder if a level shifter would give a squarer wave_." Following it with a 2nd inverter will give a squarer wave.
@Matt Venn: "_I want to learn how to buffer a node"._ Use a buffer amplifier, which is an op-amp configured as a unity-gain amplifier, also known as a "voltage follower". These are easy to make; you start with a simple amplifier circuit. Connect the amplifier's output to its own negative input, creating a negative feedback loop. Connect the signal you're buffering to the amp's positive input. Now your signal is only loaded by a single transistor gate, and the amplifier can provide a lot of current into whatever you're loading the analog pin with. The amplifier will copy the input voltage to the output with a small error, because the gain of the amplifier isn't exactly 1, but rather (1 - 1/_A_) where A is the open-loop gain of the amplifier. The higher the open-loop gain of the amp, the closer the output voltage follows the input voltage. If the voltage you're buffering doesn't get close to ground, then the amplifier can be the simplest differential-pair circuit with 5 transistors (differential pair, current sink, and current mirror).
👍 1
✅ 1
s
Another possible implementation for an oscillator is this one. A SR latch charges alternatively two capacitors C1,C2 with resistances R1,R2 from 0 to Vcc/2. The Vcc/2 threshold is the input threshold that will flip the SR latch. The oscillator period will thus be 
2 * RC *ln(2)
, depending on the value of identical capacitors (C1 and C2) and identical resistances (R1 and R2) but not on the supply voltage level and transistor parameters (only to a first order approximation of course). You see simulated period at 1.7V and 1.9V Vcc is almost identical.
👍 1
c
With the kind of minimalistic mindest that gets confused, even offended, by any configuration option of a critical infrastructure design tool (
xschemrc
, nudge nudge, wink wink) that may lead to inconsistencies between different people using it, I'd want to challenge you to eliminate from this schematic any component that is not absolutely necessary and keep only MOS transistors, and as few of them as possible. [Hint: Size matters] As for expertise in critical design tool infrastructure: This looks like an excellent example for mixed-signal simulation. Is the repository with the design files openly available on github (or similar)?
One more thing: How would you add a graph with the transient current consumption of the digital NAND gates at the bottom left BB= VCC ⊼ B AB= ENAB ⊼ A across PVT corners, using your tool chain?
s
You can pick the drain currents of the 2 parallel MOS of the nand gates and add them up. For low power you can scale down gates W/L or use low power comparators between caps and latch, but this is just a one shot stupid example. The stupid example circuits are in https://github.com/StefanSchippers/xschem_sky130/tree/main/sky130_tests
⚡ 1
c
Thanks!
Copy code
~/EDA/efabless/chipalooza2024/xschem_sky130$ du -h -d 2 .
15M	./.git/objects
8,0K	./.git/info
28K	./.git/refs
4,0K	./.git/branches
56K	./.git/hooks
32K	./.git/logs
15M	./.git
2,6M	./xschem_verilog_import
30M	./decred_hash_macro
612K	./sky130_fd_pr/doc
928K	./sky130_fd_pr
32K	./scripts
112K	./mips_cpu
372K	./stdcells/doc
688K	./stdcells
528K	./sky130_stdcells/doc
16K	./sky130_stdcells/scripts
2,3M	./sky130_stdcells
1,5M	./sky130_tests
53M	.
What eats up so much memory in decred_hash_macro (and why)? As for the 
sky130_tests
, are those the circuits made available through 
top.sch
(i.e., are they already available with the 
xschem
build)? As for sizing transistors, this only helps you so much … in addition to the digital switching current spikes, you also have current through the digital NAND gate, that changes a lot across PVT corners, as the oscillator capacitor charges slowly. Looks perfectly adequate in a proof-of-xschem-concept schematic, but on silicon, it may be a bit of an uncontrollable power hog. What would a transistor-level design of, say, a CD4093A look like, anyhow? And how would you integrate up the charge (energy) consumption over one oscillation cycle in xschem+ngspice??
s
in the graphs above a running average over one period is calculated. This gives the exact average current from Vcc after one elapsed period. 
"avg current; I(vvcc) 46.3n ravg()"
This expression in waveform dialog box will calculate the running average of 
I(vvcc)
(supply current) over one oscillation period, thus giving a fairly precise value of average current, as long as the integration period is equal to the oscillation period. Otherwise you can use the simpler avg() function and integrate over a long period.
💡 1
c
Do I have a choice how to compute mathematical expressions from voltages and currents, depending on whether I want to use conventional math notation (use 
ngspice let
) or speak hsilop 🇲🇨 (use 
xschem
expression evaluation)? And which syntax will CACE understand to do the bean counting??
s
What eats up so much memory in decred_hash_macro (and why)?
This was an import of a big (for viewing as a schematic) RTL synthetized design. https://github.com/StefanSchippers/xschem_sky130/blob/main/decred_hash_macro/README.md I used to verify if xschem was still able to propagate logic levels on its own (blue = 0, red=1) thru the digital gates as a stress test.
c
Thanks! Anyhow, is the oscillator toy schematic available on an open github, so I could track your progress in (almost) real time?
s
Do I have a choice how to compute mathematical expressions from voltages and currents,
depending on whether I want to use conventional math notation (use 
ngspice let
)
I think you should use what is the best for your need. Ngspice processing happens during simulation, xschem has merely some data post processing abilities. I was bored of running again a long simulation just because I forgot to add a .meas line or create a instantaneous power vector, so some simple calculations can be done on the raw data. Ngspice also can do post-sim processing, like plot i(vvcc) *vcc For more advanced needs I think there are also python libs with more esotheric signal processing functionality. So there are various options.
💡 1
Anyhow, is the oscillator toy schematic available on an open github, so I could track your progress in (almost) real time?
yes --> https://github.com/StefanSchippers/xschem_sky130/blob/main/sky130_tests/sky130_oscillator.sch
I have resized a bit the gates and even in the 
ff
process corner given 46uA the average current spent to charge the capacitors the overall circuit takes 50uA at 1.9V. For 1.8V designs where Vcc =~= vthn + vthp the dc consumption in cmos gates is quite low using appropriate sizing. You can go lower by shrinking the capacitors, until parasitics remain a a small fraction to have predictable results.
c
@Stefan Schippers, took me a while to get around trying this out. xschem opens and simulates both from your repository and mine, but the waves don't load. Is my xschem putting 
/home/cmaier/.xschem/simulations/sky130_oscillator.raw
in an unexpected place? Question with the very basic schematic I'm working on right now: How do I get the expression ngspice 40 -> 
plot xlog gm_id vs @m.xm1.msky130_fd_pr__nfet_01v8[id]
past the @ evaluation in xschem? This clobbers up variable definitions. I'm also wondering if I can suppress arithmetic evaluation of computed signal names like gm/Id .
I see you do
Copy code
alterparam vcc=1.9
reset
set appendwrite
between simulation runs. Can you also do this with • temperature? • device sizes?? • model corners???
t
@Christoph Maier: _Device sizes_: Yes. _Temperature_: I think so. _Model corners_: I don't think so, because I don't think there is an interactive command that is equivalent to the ".lib" statement.
l
@Mitch Bailey is probably right. A level shifter would be a nicer solution, as you already have differential oscillating voltages. Try to avoid inverters as level shifters as much as possible. They don't just use extra power, but also will output more noise, if their inputs and outputs aren't at the rail voltages.
c
Making baby steps towards really understanding PVT runs and parameter variations on the lowest possible level: https://bitbucket.org/cmucsd/transistorcharacterization/src/transistorcharacterization/xschem/ … with some inspiration of others' very helpful stuff. https://bitbucket.org/cmucsd/transistorcharacterization/commits/4f1a065c34de7502fb4f14622cf9e2335ed24ec8
@Luis Henrique Rodovalho, generally, rigid interface specifications between building blocks tend to blow up the state space of a circuit, because now you need to factor in the feelings of others when you peek out of your assigned box and look how others choose to do things. This generally requires "Awareness Teams" that tend to exhort designers not to disturb others' circles (and circuits), and mandate "trigger warnings". So I'll forward you Mr. Schmitt's trigger warning 😜: https://e2e.ti.com/support/logic-group/logic/f/logic-forum/91055/classic-4093-schmitt-trigger-gated-oscillator-trouble
s
@Christoph Maier
xschem opens and simulates both from your repository and mine, but the waves don't load.
Is my xschem putting
/home/cmaier/.xschem/simulations/sky130_oscillator.raw
in an unexpected place?
if simulator runs first try to figure out where this file is. At the xschem prompt doing: 
puts $netlist_dir
will tell you where the sim stuff is written.
c
@Stefan Schippers, I know (or can 
find ~ -name sky130_oscillator.raw
) where the simulation data ends up. But how and where, exactly, do I tell 
xschem
where to find it? If there are several possible places and workarounds to tell 
xschem
where the file is, which of them is the one intended by the lead designer?
s
@Christoph Maier xschem produces the netlist and runs the simulator in the directory set into 
$netlist_dir
. This is by default 
~/.xschem/simulations
. when you run a simulation schem forks the simulator process into 
$netlist_dir
, so the simulator will find all its needed files without funky path names. You can set this variable in your xschemrc file to change the destination. You can then load sim data in xschem by doing 
xschem raw read $netlist_dir/circuit_name.raw tran
c
@Stefan Schippers, I have 
sky130_oscillator.raw
files both as 
~/.xschem/simulations/sky130_oscillator.raw
and as 
~/EDA/efabless/chipalooza2024/xschem_sky130/sky130_tests/simulation/sky130_oscillator.raw
, and your schematic displays neither of them. Your 
launcher.sym
device contains
Copy code
name=h5
descr="load waves" 
tclcommand="xschem raw_read $netlist_dir/sky130_oscillator.raw tran"
Do I need to manually push a button or click on the launcher, or does it execute automatically? Where would I find an error message if the launcher fails to find the file?? Can I edit the file name in the launcher in your schematic on the fly, or would I have to re-netlist and re-simulate???
@Stefan Schippers, your simulation works just fine, the waveforms in 
sky130_oscillator.raw
are all there and visible with gaw, and in gaw, I can even plot what I expect to be the worst cross-currents in the digital gates fed non-digital inputs (which I haven't found out how to do in xschem, because xschem interprets 
@
as instruction and clobbers up the signal name), but I can't convince your xschem schematic to put the data into the graphs. The chokepoint are probably your undocumented implicit assumptions how xschem is supposed to do things.
s
You can plot @ variables with no problem For location of simulation files --> https://xschem.sourceforge.io/stefan/xschem_man/netlisting.html
c
The one chokepoint here is that when I click on the load launcher arrow, nothing happens. I find the waveforms and can plot them from gaw, but not in xschem. This is probably an undocumented installation dependency deeply buried in the xschem code base.
s
Use the 
Waves
menu: 
Waves -> Tran->
find the 
sky130_oscillator.raw
file with the file browser -> 
Open
https://xschem.sourceforge.io/stefan/xschem_man/tutorial_ngspice_backannotation.html "_To avoid the need of typing commands in the xschem console a launcher component devices/launcher.sym can be placed with the tcl command for doing the annotation. Just do a Ctrl-Click on it to trigger the annotation_." the command to load a raw file so it can be displayed in graphs is: 
xschem raw read $netlist_dir/sky130_oscillator.raw tran
this command should be placed in the launcher: 
tclcommand="xschem raw read $netlist_dir/sky130_oscillator.raw tran"
Doing a 
Control + Left mouse button click
triggers the action.
12 Views
Open in Slack
PreviousNext
Powered by