Just one more note/observation about the MOS models. They seem to have a strong degree of width/finger dependence that I haven't seen before in 130nm and it is quite difficult to design anything systematically with this behavior. For example, both the threshold voltage and overlap capacitances vary strongly with absolute width and number of gates. The example data below is for an LV NMOS with W=10u. One device has ng=1, the other has ng=4. There is a 30 mV difference in Vt (I can see some applications for this if it is real...). The difference in overlap capacitance is 1.5fF, which is almost 50% of the intrinsic cgs. Also, the overlap cap of the device with ng=4 is smaller, which I don't understand intuitively (I'd probably expect the opposite due to more fringing).

PSPNQS103VA: A simulator independent device loaded with OSDI
   device n.xm2.nsg13_lv_nmos n.xm1.nsg13_lv_nmos
   model xm2:sg13g2_lv_nmos_ps xm1:sg13g2_lv_nmos_ps
  _mfactor          1          1
     m          1          1
     l       1.3e-07       1.3e-07
     w        1e-05       2.5e-06
...
     as       3.4e-12      6.625e-13
     ps      2.068e-05       4.28e-06
     ad       3.4e-12       4.75e-13
     pd      2.068e-05       2.88e-06
    mult          1          4
...
    ids     0.000304098      0.00022106
...
    vds         0.6         0.6
    vgs         0.6         0.6
    vsb          0          0
    vto       0.419227       0.44854 *****
    vts       0.419226       0.448539
    vth       0.417579       0.446981
    vgt       0.182421       0.153019
    vdss       0.202016       0.188123
    vsat       0.397984       0.411877
     gm      0.00281996      0.00220814
    gmb     0.000317923     0.000264871
    gds     0.000144924     0.000122579
    gjs     1.85502e-14      1.7889e-14
    gjd     9.11219e-15     8.64268e-15
    cdd     2.91916e-17     2.79445e-17
    cdg     1.37934e-15     1.26091e-15
    cds     -1.50079e-15     -1.3836e-15
    cdb     1.50637e-16      1.5064e-16
    cgd     3.03249e-17     2.95889e-17
    cgg     3.88204e-15     3.71399e-15
    cgs     3.54412e-15     3.32043e-15
    cgb     3.07594e-16     3.63968e-16
    csd     -6.23079e-18     -7.12925e-18
    csg     2.12495e-15     2.01909e-15
    css     2.35104e-15     2.25364e-15
    csb     2.32324e-16     2.41682e-16
    cbd     5.09747e-18     5.48484e-18
    cbg     3.77743e-16     4.33993e-16
    cbs     3.07714e-16     3.16812e-16
    cbb     6.90555e-16      7.5629e-16
    cgsol     6.31456e-15      4.8275e-15 ******
    cgdol      6.0478e-15     4.55994e-15 ******
    cjs      3.9791e-15     3.13764e-15
   cjsbot     3.39813e-15     2.64854e-15
   cjsgat      3.0504e-16     3.06867e-16
   cjssti     2.75927e-16     1.82225e-16
    cjd     3.26029e-15      1.8401e-15
   cjdbot     2.76558e-15     1.54547e-15
   cjdgat     2.61567e-16     2.63133e-16
   cjdsti     2.33141e-16     3.14937e-17
    weff      1.002e-05       2.52e-06
    leff      7.1154e-08      7.1154e-08
     u       19.4583       18.0141
    rout       6900.19       8158.04
   vearly       2.09834       1.80342
    beff      0.0182765      0.0188821
    fug     2.76287e+10     2.68243e+10
     rg       10.0192       10.0192

Hi Boris, I have not worked with the MOS devices in this kit yet, so take my questions with a grain of salt. 1. The mult variable, is this actually nr of fingers? I am asking because in other kits, and esp RF models, the mult variable usually is a non layout parameter, in the sense that it doesnt change the device, but it tells the model how many of those devices is in the same p or n well. Might this not be the same? That would make a lot of sense, as the actuall width of your transistor is still 2.5um, but you are telling it there is four more transisotors nearby,

There is no well proximity modeled here (that's a post-layout issue; well distance is unknown here). Vth clearly should change for very small W due to the narrow width effect, but I don't see how 30 mV for such huge unit devices is reasonable. The MOS models use ng (number of gates) as a parameter. If you enter W=10u and ng=4, you get 4 devices that are 2.5um each. This is nothing I did; it's how the model is implemented and presented to the user.

@Boris Murmann, Did you extract the circuit values you show at the top here at a specific bias condition?

There is no extraction here, just a simple op simulation. There is also no Miller effect to speak of (it's not how .OP capacitances are calculated). These are just two devices sitting in a circuit by themselves with constant VGS and VDS; you can see this from the op output. There is really no black magic here, I promise.

Cool, then I have depleted my knowledge 🙂 Sorry. 😞

@Boris Murmann thank you for pointing out this issue. I will check with the model developers the results. Anyway there are some issues with the parameters like m, mfact which were are not correctly propagated across the model. In your case there the mult parameter is the one that seems to represent the number of gates/fingers so maybe there is something wrong with naming convention. Let me verify this.

@Krzysztof Herman, Just a quick question on this, is the "Mult" not a variable you set for simulation only, to include a few extra parasitics due to device proximity? i.e. if you have 4 closely spaced NMOS transistors in the same well, does this variable not allow you to set it to 4 and get a closer (un-extracted) performance to easily simulate designs, that you need to verify later with an extraction tool?

@RikusNel PSP103 documentation says that mult is the number of devices in parallel

Uhm, I might have communicated my point wrong. Yes. I meant in parallel and close. It does not physically add the other devices in layout, but it tells the simulator you've added this many in parallel, close together. (This was the case on a different PDK I worked with).

image.png

@Krzysztof Herman unfortunately the dev branch merge did not address my issue. I see that the main change is to replace ng with ng*m. In my simulation, m=1, so there is no effect. Just to re-cap the two issues: 1. There seems to be too strong of a width dependence in Vt. This is also documented here: https://github.com/IHP-GmbH/IHP-Open-PDK/issues/46. It is well understood that Vt will change for very narrow devices. But the present models show significant changes in Vt versus W for wide devices. I would expect the curve to flatten s shown here: https://www.semanticscholar.org/paper/Implications-of-Small-Geometry-Effects-on-%24g_m-I[…]erreira/7982fbeb3a43c594a244923438360aa5ebd1b478/figure/4. 2. The size of the overlap caps and how they scale with W and ng. For a 10/0.13 NMOS, the simulated cgdol=6fF, while 3.6fF is expected from the process spec (see below). The simulated value changes to 4.6fF with ng=4, which is hard to explain when I think about the actual layout. I can see how some deltaW affects this in a fingered device, but in reality splitting up a device does not give you smaller caps due to fringing. I suspect something is wrong with the underlying equations in terms of absolute numbers and scaling behavior.

@Boris Murmann could you please open a github issue on that, it will be way easier to track this.

OK, will do.

@Boris Murmann I have just cross checked your test case using spectre and the results are the same so the issue can have the root cause in the actual model parameters extracted from the measurements.

@Krzysztof Herman Thank you. I agree that this is likely a parameter extraction issue. I added this observation to the relevant GitHhb issues threads so that it can be tracked.