@jeffdi is there example code for hkspi? I want to receive and transmit data using it. this is my code attempt.I am trying to transmit 0xab

You can't use the housekeeping SPI like that. The

reg_hkspi_irq

is just a register where you can force an IRQ signal to the CPU by setting a bit in an SPI register.

reg_hkspi_status

is a reserved register that doesn't do anything. Housekeeping is a slave SPI only and cannot be configured as a master.

I can provide the clk and cs from master outside, but slave data can be read by master over sdi , right @Tim Edwards @Matt Venn?. Issue is my main master spi pins I have used for other purpose, and I need to communicate with the management area. Why can’t it work as normal slave?

I'm still not clear what you are trying to do. If you want to use an SPI to transmit a serial data byte like 0xab from Caravel to another device, then you have to use the SPI master, an SPI master that you have implemented in the user project, or emulate an SPI master through software. The housekeeping SPI is a slave only and cannot send data.

@Tim Edwards @Matt Venn below is the diagram for clarification, and while flashing the chip, where is the data stored from ftdi to slave spi if there is no save register to store. is it to do with pass through mode?

@samarth jain: I think I now understand what you are doing. The main problem with that setup is that there are no "general purpose" registers in housekeeping that are available just to store and retrieve data (probably we should have added some). However, there is something close to it, which is a number of registers that have no effect on anything unless something else is enabled. Here are some examples: (1) DLL trim (3 bytes, only used when the DLL is enabled and running in DCO mode) (2) GPIO configure (this is a 12-bit configuration for 38 GPIO channels, so every other register is a full byte, and there are 38 of them. The GPIO configure bits in housekeeping are used initially to set the GPIO configuration, but after that they are free to be used for data) You can read/write to these registers from either the CPU on the wishbone bus, or through the SPI (for access from your FPGA). The addresses are mapped differently for SPI (1-byte address) vs. wishbone (4-byte address): (1) DLL trim: SPI registers 0x0d, 0x03, and 0x0f = Wishbone address 0x2610001c to 0x2610001e (do a 32-bit read or write at address 0x2610001c, look only at lower 24 bits) (2) GPIO configure: SPI registers 0x1e, 0x20, 0x22, 0x24, ..., 0x66, 0x68 = Wishbone addressses 0x26000024, 0x26000028, 0x2600002c, ..., 0x260000b4, 0x260000b8, look only at lower 8 bits of each word) Does that make sense to you?

ok @Tim Edwards,pls do consider general purpose registers update in next april tapeouts and let me know how I can help. I think this way is very slow for a spi as each address register needs serial write.Already I tried spi and its max speed i could push was 500KHz. is there plans for more buses like pci or ethernet?

You'll have to take that up with Mohamed Shalan and the digital design team, because I don't have much impact on the digital design. I thought the timing constraints on the SPI signaling were the same as for the CPU core, which is at least 25MHz. But I have not done a performance limit test of the SPI.