Thanks Tim, sorry I misunderstood. Thought you were just letting me know that it works. Here is the output netlist after CACE runs the DAC example, which I found inside the

sky130_ef_ip__rdac3v_8bit/ngspice

directory, following your instructions to `Keep simulation files`:

** sch_path: /home/rtsang/chipalooza/sky130_ef_ip__rdac3v_8bit/cace/dccurrent_vdd.sch
**.subckt dccurrent_vdd
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VVlow Vlow VSUB DC 0
VVhigh Vhigh VSUB DC 3.3
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Vvss vss VSUB DC 0
Rout out VSUB 100000000.0 m=1
Cout out VSUB 1e-13 m=1
Vdvss dvss VSUB DC 0
Vvdd vdd VSUB DC 3.3
Vdvdd dvdd VSUB DC 1.8
RSUB VSUB GND 0.01 m=1
XDUT dvdd vss dvss vdd b0 Vhigh b1 b2 b3 out b4 b5 ena b6 b7 Vlow sky130_ef_ip__rdac3v_8bit
**** begin user architecture code

.control
op
set wr_singlescale
wrdata ngspice/Idd_enabled_1.data -I(Vvdd)
quit
.endc

Clearly something to do with the expression evaluation. Let me think up something that will help pin it down. What version of python do you have?