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<@U016EM8L91B> Hi Tim, when running the CACE examp...
# chipalooza
r
@Tim Edwards Hi Tim, when running the CACE example of sky130_ef_ip__rdac3v_8bit I’m running into an issue where the expanded input bits b[7:0] are not showing up in the .spice netlist (can see eight ‘?’ that look like placeholders in the netlist). I am guessing CACE is supposed to sweep between min/max digital values by setting the 8 voltage sources accordingly. Tried the INL, DNL cases and all doing the same. Just cloned and installed cace today and sky130_ef_ip__rdac3v_8bit tonight. Love the bit expansion/enum feature. Will be awesome if it works. Thanks.
t
I haven't seen any problem with the DAC. If I select "Settings->Keep simulation files" and then do "Simulate", this is what I get for INL_1.spice:
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** sch_path: /home/tim/gits/sky130_ef_ip__rdac3v_8bit/cace/voltage_output.sch
**.subckt voltage_output
VVDAC7 b7 VSUB DC 0.0
VVDAC1 b1 VSUB DC 0.0
VVDAC2 b2 VSUB DC 0.0
VVDAC3 b3 VSUB DC 0.0
VVDAC4 b4 VSUB DC 0.0
VVDAC5 b5 VSUB DC 0.0
VVDAC6 b6 VSUB DC 0.0
VVDAC0 b0 VSUB DC 0.0
VVlow Vlow VSUB DC 0
VVhigh Vhigh VSUB DC 3.3
Vena ena VSUB DC 1.8
Vvss vss VSUB DC 0
Rout out VSUB 100000000.0 m=1
Cout out VSUB 1e-13 m=1
Vdvss dvss VSUB DC 0
Vvdd vdd VSUB DC 3.3
Vdvdd dvdd VSUB DC 1.8
RSUB VSUB GND 0.01 m=1
XDUT dvdd vss dvss vdd b0 Vhigh b1 b2 b3 out b4 b5 ena b6 b7 Vlow sky130_ef_ip__rdac3v_8bit
**** begin user architecture code

.control
op
set wr_singlescale
wrdata ngspice/INL_1.data V(out)
quit
.endc



* CACE gensim simulation file INL_1
* Generated by CACE gensim, Efabless Corporation (c) 2023
* Simple output voltage measurement for a DAC (DC operating point)

.include ./netlist/schematic/sky130_ef_ip__rdac3v_8bit.spice

.include /usr/local/share/pdk/sky130A/libs.ref/sky130_fd_sc_hvl/spice/sky130_fd_sc_hvl.spice

.lib /usr/local/share/pdk/sky130A/libs.tech/combined/sky130.lib.spice tt

.option SEED=12345
.option TEMP=27
* Flag unsafe operating conditions (exceeds models' specified limits)
.option warn=1


**** end user architecture code
**.ends
.GLOBAL GND
.end
r
Thanks Tim. The weird thing is the sky130_ef_ip__instramp example works fine, I can see most tests pass and some fails. But for the DAC, the voltage sources of b[7:0] and 'ena' just aren't generating. When
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git clone <https://github.com/RTimothyEdwards/sky130_ef_ip__rdac3v_8bit>
Cloning into 'sky130_ef_ip__rdac3v_8bit'...
remote: Enumerating objects: 109, done.
remote: Counting objects: 100% (109/109), done.
remote: Compressing objects: 100% (71/71), done.
remote: Total 109 (delta 49), reused 93 (delta 33), pack-reused 0
Receiving objects: 100% (109/109), 321.73 KiB | 1.67 MiB/s, done.
Resolving deltas: 100% (49/49), done.
rtsang@ajacci9:~/chipalooza$ cd sky130_ef_ip__rdac3v_8bit/
rtsang@ajacci9:~/chipalooza/sky130_ef_ip__rdac3v_8bit$ cace-gui
Creating simulation path ngspice
Checking for out-of-date schematic-captured netlists.
Forcing regeneration of schematic-captured netlist.
Generating simulation netlist from schematic. . .
Calling xschem to generate netlist
Error: undriven node: #net12
Warning: shorted output node: Vhigh
Warning: shorted output node: out_unbuf
Warning: shorted output node: #net9
Warning: shorted output node: #net31
Warning: shorted output node: #net32
Warning: shorted output node: #net33
Warning: shorted output node: #net34
Warning: shorted output node: #net35
Warning: shorted output node: #net36
Warning: shorted output node: #net53
Warning: shorted output node: #net54
Warning: shorted output node: #net55
Warning: shorted output node: #net56
Warning: shorted output node: #net57
Warning: shorted output node: #net58
Warning: shorted output node: #net59
Warning: shorted output node: #net60
Warning: shorted output node: out
Warning: shorted output node: #net10
Warning: shorted output node: #net11
Warning: shorted output node: #net12
Warning: shorted output node: #net13
Warning: shorted output node: #net14
Warning: shorted output node: #net15
Warning: shorted output node: #net16
Warning: shorted output node: #net17
Warning: shorted output node: #net8
Warning: shorted output node: #net9
Error: overlapped instance found: R9(sky130_fd_pr/res_high_po_0p35.sym) -> R8
Warning: shorted output node: #net10
Warning: shorted output node: #net11
Warning: shorted output node: #net12
Warning: shorted output node: #net13
Warning: shorted output node: #net14
Warning: shorted output node: #net15
Warning: shorted output node: out
Warning: shorted output node: #net8
Warning: shorted output node: #net9
Error: overlapped instance found: R9(sky130_fd_pr/res_high_po_0p35.sym) -> R8
Checking for out-of-date testbench netlist dccurrent_vdd.spice.
Generating testbench netlist dccurrent_vdd.spice from schematic. . .
Calling xschem to generate netlist
Error: undriven node: #net12
Warning: shorted output node: Vhigh
Warning: shorted output node: out_unbuf
Warning: shorted output node: #net9
Warning: shorted output node: #net31
Warning: shorted output node: #net32
Warning: shorted output node: #net33
Warning: shorted output node: #net34
Warning: shorted output node: #net35
Warning: shorted output node: #net36
Warning: shorted output node: #net53
Warning: shorted output node: #net54
Warning: shorted output node: #net55
Warning: shorted output node: #net56
Warning: shorted output node: #net57
Warning: shorted output node: #net58
Warning: shorted output node: #net59
Warning: shorted output node: #net60
Warning: shorted output node: out
Warning: shorted output node: #net10
Warning: shorted output node: #net11
Warning: shorted output node: #net12
Warning: shorted output node: #net13
Warning: shorted output node: #net14
Warning: shorted output node: #net15
Warning: shorted output node: #net16
Warning: shorted output node: #net17
Warning: shorted output node: #net8
Warning: shorted output node: #net9
Error: overlapped instance found: R9(sky130_fd_pr/res_high_po_0p35.sym) -> R8
Warning: shorted output node: #net10
Warning: shorted output node: #net11
Warning: shorted output node: #net12
Warning: shorted output node: #net13
Warning: shorted output node: #net14
Warning: shorted output node: #net15
Warning: shorted output node: out
Warning: shorted output node: #net8
Warning: shorted output node: #net9
Error: overlapped instance found: R9(sky130_fd_pr/res_high_po_0p35.sym) -> R8
Evaluating electrical parameter Idd_enabled
Launching Simulations
Total files to simulate: 1
Files to simulate method Idd_enabled: 1
Copying ngspice configuration file from PDK.
Running: ngspice  ngspice/Idd_enabled_1.spice
Current working directory is: /home/rtsang/chipalooza/sky130_ef_ip__rdac3v_8bit
Warning: Unusual leading characters like '?' or others out of '= [] ? () & % $"!:,\f'
    in netlist or included files, will be replaced with '*'.
    Check line no 3:  ?

Warning: redefinition of .subckt sky130_ef_ip__rdac3v_8bit, ignored
Warning: redefinition of .subckt dac_half, ignored
Warning: redefinition of .subckt passtrans, ignored
Warning: redefinition of .subckt level_shifter, ignored
Warning: redefinition of .subckt follower_amp, ignored
Warning: redefinition of .subckt dac_column_dummy, ignored
Warning: redefinition of .subckt dac_column, ignored
******
** ngspice-42 : Circuit level simulation program
After a fresh clone and running cace-gui, clicking on the Idd simulation, I get the output above. Towards the end of the log the warning probably what's causing it not to work. In the spice file:
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Warning: Unusual leading characters like '?' or others out of '= [] ? () & % $"!:,\f'
Any ideas? Is there any setup requirement for .spiceinit or xschemrc other than setting the PDK_ROOT and PDK env variables? Though I may have messed something up when setting up CACE earlier using make, but I tied it on another computer that hasn't see CACE and same result. Thanks.
t
@Robin Tsang: The weird thing is that I have exactly the same output as you up to "Total files to simulate" . . . If you didn't change the characterization file, then it should be counting three files to simulate. Can you do what I mentioned above about checking the box in "Settings" for "Keep simulation files", and then post the contents of file 
ngspice/Idd_enabled_1.spice
?
Also post the file 
cace/dccurrent_vdd.spice
which is the template for generating 
ngspice/Idd_enabled_X.spice
.
r
Sorry for the creating the new thread, user error. Here are both together for comparison. Thanks. Contents of `cace/dccurrent_vdd.spice`:
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** sch_path: /home/rtsang/chipalooza/sky130_ef_ip__rdac3v_8bit/cace/dccurrent_vdd.sch
**.subckt dccurrent_vdd
?
?
?
?
?
?
?
?
VVlow Vlow VSUB DC {Vlow}
VVhigh Vhigh VSUB DC {Vhigh}
?
Vvss vss VSUB DC {Vvss}
Rout out VSUB {Rout} m=1
Cout out VSUB {Cout} m=1
Vdvss dvss VSUB DC {Vdvss}
Vvdd vdd VSUB DC {Vvdd}
Vdvdd dvdd VSUB DC {Vdvdd}
RSUB VSUB GND 0.01 m=1
XDUT dvdd vss dvss vdd b0 Vhigh b1 b2 b3 out b4 b5 ena b6 b7 Vlow sky130_ef_ip__rdac3v_8bit
**** begin user architecture code

.control
op
set wr_singlescale
wrdata {simpath}/{filename}_{N}.data -I(Vvdd)
quit
.endc
Contents of `ngspice/Idd_enabled_1.spice`:
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** sch_path: /home/rtsang/chipalooza/sky130_ef_ip__rdac3v_8bit/cace/dccurrent_vdd.sch
**.subckt dccurrent_vdd
?
?
?
?
?
?
?
?
VVlow Vlow VSUB DC 0
VVhigh Vhigh VSUB DC 3.3
?
Vvss vss VSUB DC 0
Rout out VSUB 100000000.0 m=1
Cout out VSUB 1e-13 m=1
Vdvss dvss VSUB DC 0
Vvdd vdd VSUB DC 3.3
Vdvdd dvdd VSUB DC 1.8
RSUB VSUB GND 0.01 m=1
XDUT dvdd vss dvss vdd b0 Vhigh b1 b2 b3 out b4 b5 ena b6 b7 Vlow sky130_ef_ip__rdac3v_8bit
**** begin user architecture code

.control
op
set wr_singlescale
wrdata ngspice/Idd_enabled_1.data -I(Vvdd)
quit
.endc
t
Oh, interesting. I was not expecting that. Let me investigate. . .
What version of xschem do you have?
So what appears to be happening is that xschem is seeing the 
[ ... ]
notation in the schematic and instead of copying it verbatim to the output, it is trying to evaluate it with Tcl. Either the behavior is xschem-version-dependent, or else there is an xschem setting being applied that I don't know about.
r
Using xschem ver 3.4.4 There is no xschemrc in the 
sky130_ef_ip__rdac3v_8bit
base directory (cace is run right after cloning the DAC example, no edits or changes), and I also don't have an xschemrc in ~/.xschem/ either.
Just as an FYI, the use-case is to set the trip voltages of the brown-out/overvoltage circuits which are 3/4-bit binary values decoded into 8/16 trip voltages. Thanks again .
Python 2.7.18 Python 3.10.12
t
Your last post exonerated python. The issue is happening when xschem writes output. The xschemrc file is passed to xschem on the command line and is taken from the PDK. But I don't expect that to be an issue. This is very puzzling. If you just 
cd
to 
cace
and run xschem manually on 
dccurrent_vdd.sch
(using the xschemrc file from the PDK), and write a netlist, does that netlist look the same?
I have xschem version 3.4.5. I don't think anything happened in the last revision that would impact the output, but it might be worth checking.
r
Running 
xschem dccurrent_vdd.sch
in the directory 
sky130_ef_ip__rdac3v_8bit/cace
brings up xschem that shows a bunch of missing symbols (all the xschem devices that come with xschem like voltage sources), but the one symbol working is 
sky130_ef_ip_rdac3v_8bit
. If I put an 
xschemrc
in 
sky130_ef_ip__rdac3v_8bit/cace
and re-run 
xschem dccurrent_vdd.sch
in said directory, all the symbols work (see pictures).
xschem 3.4.4 seems to be the latest version available from https://github.com/StefanSchippers/xschem
t
I just do a git pull from the repository, build, install, and run 
xschem --version
and it reports "3.4.5". . .
Yes, now based on your previous screenshot where you got xschem to work. . . what do you get for a netlist output from that?
It's not possible to see from the screenshot, but the value text for each of the voltage sources generating the digital value is, e.g., 
DC [{b[0]} * {Vdvdd}]
. Xschem should be writing that out verbatim, but your netlist output ends up as 
?
. . . The whole thing is 
?
and not just the expression. It should have shown up in the netlist as 
VVDAC0 b0 VSUB DC [{b[0]} * {Vdvdd}]
.
r
Yes, its 3.4.5, I was confused. xschem is now 3.4.5. I deleted cace/dccurrent_vdd.spice and re-ran cace-gui with xschemrc inside the cace directory. It generated what appears correct: Contents of `cace/dccurrent_vdd.sch`:
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** sch_path: /home/rtsang/chipalooza/sky130_ef_ip__rdac3v_8bit/cace/dccurrent_vdd.sch
**.subckt dccurrent_vdd
VVDAC7 b7 VSUB DC [{b[7]} * {Vdvdd}]
VVDAC1 b1 VSUB DC [{b[1]} * {Vdvdd}]
VVDAC2 b2 VSUB DC [{b[2]} * {Vdvdd}]
VVDAC3 b3 VSUB DC [{b[3]} * {Vdvdd}]
VVDAC4 b4 VSUB DC [{b[4]} * {Vdvdd}]
VVDAC5 b5 VSUB DC [{b[5]} * {Vdvdd}]
VVDAC6 b6 VSUB DC [{b[6]} * {Vdvdd}]
VVDAC0 b0 VSUB DC [{b[0]} * {Vdvdd}]
VVlow Vlow VSUB DC {Vlow}
VVhigh Vhigh VSUB DC {Vhigh}
Vena ena VSUB DC [{ena} * {Vdvdd}]
Vvss vss VSUB DC {Vvss}
Rout out VSUB {Rout} m=1
Cout out VSUB {Cout} m=1
Vdvss dvss VSUB DC {Vdvss}
Vvdd vdd VSUB DC {Vvdd}
Vdvdd dvdd VSUB DC {Vdvdd}
RSUB VSUB GND 0.01 m=1
XDUT dvdd vss dvss vdd b0 Vhigh b1 b2 b3 out b4 b5 ena b6 b7 Vlow sky130_ef_ip__rdac3v>
**** begin user architecture code

.control
op
set wr_singlescale
wrdata {simpath}/{filename}_{N}.data -I(Vvdd)
quit
.endc
Contents of ngspice/Idd_enabled_1.spice:
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** sch_path: /home/rtsang/chipalooza/sky130_ef_ip__rdac3v_8bit/cace/dccurrent_vdd.sch
**.subckt dccurrent_vdd
VVDAC7 b7 VSUB DC 0.0
VVDAC1 b1 VSUB DC 0.0
VVDAC2 b2 VSUB DC 0.0
VVDAC3 b3 VSUB DC 0.0
VVDAC4 b4 VSUB DC 0.0
VVDAC5 b5 VSUB DC 0.0
VVDAC6 b6 VSUB DC 0.0
VVDAC0 b0 VSUB DC 0.0
VVlow Vlow VSUB DC 0
VVhigh Vhigh VSUB DC 3.3
Vena ena VSUB DC 1.8
Vvss vss VSUB DC 0
Rout out VSUB 100000000.0 m=1
Cout out VSUB 1e-13 m=1
Vdvss dvss VSUB DC 0
Vvdd vdd VSUB DC 3.3
Vdvdd dvdd VSUB DC 1.8
RSUB VSUB GND 0.01 m=1
XDUT dvdd vss dvss vdd b0 Vhigh b1 b2 b3 out b4 b5 ena b6 b7 Vlow sky130_ef_ip__rdac3v>
**** begin user architecture code

.control
op
set wr_singlescale
wrdata ngspice/Idd_enabled_1.data -I(Vvdd)
quit
.endc
The simulation still fails with 9661uA but that's mostly a different issue. Thanks!
INL is working as well. I can see the digital bits b[7:0] changing from run-to-run. Thanks a bunch. Contents of ngspice/INL_2.spice:
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** sch_path: /home/rtsang/chipalooza/sky130_ef_ip__rdac3v_8bit/cace/voltage_output.sch
**.subckt voltage_output
VVDAC7 b7 VSUB DC 1.8
VVDAC1 b1 VSUB DC 0.0
VVDAC2 b2 VSUB DC 1.8
VVDAC3 b3 VSUB DC 1.8
VVDAC4 b4 VSUB DC 1.8
VVDAC5 b5 VSUB DC 1.8
VVDAC6 b6 VSUB DC 1.8
VVDAC0 b0 VSUB DC 0.0
VVlow Vlow VSUB DC 0
VVhigh Vhigh VSUB DC 3.3
Vena ena VSUB DC 1.8
Vvss vss VSUB DC 0
Rout out VSUB 100000000.0 m=1
Cout out VSUB 1e-13 m=1
Vdvss dvss VSUB DC 0
Vvdd vdd VSUB DC 3.3
Vdvdd dvdd VSUB DC 1.8
RSUB VSUB GND 0.01 m=1
XDUT dvdd vss dvss vdd b0 Vhigh b1 b2 b3 out b4 b5 ena b6 b7 Vlow sky130_ef_ip__rdac3v_8bit
**** begin user architecture code

.control
op
set wr_singlescale
wrdata ngspice/INL_2.data V(out)
quit
.endc
t
Conclusion then is that only the most recent xschem works correctly on this output? That's likely; Stefan Schippers made some related change, but I hadn't tested an earlier version of xschem on these testbenches. I may need to do tool version checking on startup of CACE.
r
It seems that way, because I went ahead and deleted 
xschemrc
and all the .spice files from the 
sky130_ef_ip_rdac3v_8bit/cace
directory, then deleted the .spice files from the 
sky130_ef_ip_rdac3v_8bit/ngspice
, re-ran cace-gui, and it generated the INL_1.spice file with property b[7:0] bits/voltage sources.
t
Then I probably need both a version check on reading a datasheet plus a record in the datasheet of what tool versions were used when the datasheet was made. Which is something I should have thought about earlier.
👍 1
r
I should have updated all the tools to the latest before starting, would have saved us a lot of time today. Thank you once again for your time and patience.
t
I'm using all of you as guinea pigs for the CACE software. It's your time and patience that should be thanked. . .
👍 1
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