Hi everyone. I was implementing a digital circuit using sky130nm library file, but I am getting this error message in xterm terminal. It says "unknown subckt nand4_1". I have attached the circuit and the description of the library files I am sourcing. I checked in those library files. "nand4_1" is there but I dont know why it is saying unknown subckt

Add following line:

.include /usr/local/share/pdk/sky130B/libs.ref/sky130_fd_sc_hd/spice/sky130_fd_sc_hd.spice

hi, thanks for the reply. I changed the vgnd and vpb pin values as you told. Regarding the library file path another error occurred after the implementing your solution.

@Himanshu Singh the

code_shown.sym

values are referencing both

sky130B

and

sky130A

.

yeah. is that an issue?

@Himanshu Singh Maybe the referencing of both

sky130A

and

sky130B

is the reason for the redefinition warnings.

@Himanshu Singh I didn't see it before you are doing a .lib on the sky130_fd_sc_hd.spice file. This file must be .included. So change .lib with .include. This is what you need:

.lib /usr/local/share/pdk/sky130B/libs.tech/combined/sky130.lib.spice tt
.include /usr/local/share/pdk/sky130B/libs.ref/sky130_fd_sc_hd/spice/sky130_fd_sc_hd.spice

thanks. it worked. by the way why are we using .lib for sky130.lib.spice while we are using .include for sky130_fd_sc_hd

@Himanshu Singh the two files are different. The first one is a library format, it includes silicon device models for several process corners. The second one is just a spice netlist containing the definition of the subcircuits of all digital gates. A

.include

will read in the file into the current netlist as is with no magic or hidden things.

For the standard cells I've started adding a 'code' block with the following value:

"tcleval(
* Standard cell simulation files
.include $::SKYWATER_STDCELLS/sky130_fd_sc_hd.spice

* Power domains
VSTDCELL_PWR VPWR 0 DC 1.8
VSTDCELL_PB  VPB  0 DC 1.8
VSTDCELL_NB  VNB  0 DC 0
VSTDCELL_GND VGND 0 DC 0
.global VNB VGND VPB VPWR
)"

@Stefan Schippers thank you for the clearing the doubt. You are really helpful. i am almost at the end of my design and i need to generate a .cir file of my design on xschem. can briefly guide? I generated a .spice file

you can rename the .spice file to a .cir file or go to simulation->set top level netlist_name

@Stefan Schippers while naming the pins of logic gates what do the pin names VNB & VPB mean ? also do you know any video tutorial showing layout of a design consisting of logic gates.

@Himanshu Singh

VNB

nmos bulk connection.

VPB

pmos bulk connection.

thanks @Mitch Bailey

@Himanshu Singh usually digital designs follow a RTL-Synthesys-placement-routing flow that does not use a schematic at all. For mixed signal designs however you might want to place some standard cell logic gates in a schematic. Usually you pick the layouts of the needed cells and place them in a row or more rows, draw the vdd, gnd, vpb, vnb rails and route the signals. I don't however have tutorials on this.