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Continuing my LVS learning journey. I added a pcell generated resistor to my magic layout (manually, not by reading a spice file). I'm unable to come up with a working configuration for passing LVS

<https://github.com/mattvenn/magic_challenge/tree/main/mag>

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and tried many names, matching it exactly to the lvs spice and so on, but I can never get lvs to pass

is it possible to do with verilog? Or do I have to create a schematic spice file and use that as part of the schematic along with the verilog for netgen?

netgen accepts standalone spice files too, so a spice file with a resistor should work. With verilog only, there’s no way to specify the device parameters L and W.

For device level LVS, yes, you do want to check the size of the devices. For verilog only netlists, it’s assumed that the cells have been checked separately to ensure that the device sizes match.

<@U017X0NM2E7> <@U0172QZ342D>:  Actually, yes, it is possible to specify SPICE subcircuit parameters in verilog.  netgen accepts the use of `parameter` values in verilog for this:
```.module sky130_fd_pr__res_generic_po #(
   parameter W = 1,
   parameter L = 1
) (
   inout real A,
   inout real B
);
   // Nothing here, just a primitive placeholder
endmodule```
then call this with:
```sky130_fd_pr__res_generic_po #(
    .W(0.5),
    .L(10.0)
) my_instantiated_resistor (
    .A(ua[0]),
    .B(ua[1])
);```
The only regular issue that crops up with this method is making sure all the input/output/inout ports work together, which sometimes is impossible with analog circuits when you try to treat them like quasi-digital blocks.

I got it to work by using a spice file with netgen