@Stefan Schippers hello I was trying to simulate the transmission gate with analog input 5 in out pin I can see only 1.8v why it's happening? If I want to increase the output voltage what can I do I tried increasing the size w=20 L=1

Where are your PMOS devices bulk terminals connected to? Show us your netlist. Use printscreen instead of taking photos of your screen.

@Luis Henrique Rodovalho sorry that was the wrong picture I took I have change vcc and gnd earlier I will send the proper prtintscreen I have connected to vss pmos bulk

Ok. First of all, name all your nets. Use the input of your NOT logic gate as DIN and its output as the switch input notIN. The analog switch input is ok, but you should put some kind of load at the output node. Try a cap first. Use different kind of signals for your analog input and your digital input. For example, make a squarewave for your digital input and a ramp for your analog input.

@Rafeeq Khan Mohammed If I understand your voltage settings, 1. V1 is 1V for 500ns then drops to 0V 2. V2 is 5V for 500ns then drops to 0V 3. V3 is always 0V 4. V5 is always 1.8V If this is correct, both the nmos and pmos of the NOT may be on and the NOT output is somewhere between 0V and 1.8V. pmos turns on when the gate voltage is less than the source voltage plus Vthp which is negative. DIN causes the nmos of the switch2 to always be off, but with AIN at 5V and notIN less than 1.8V, the pmos will always be on. If you need to mix 1.8V signals with 5V signals, be sure to use a level shifter.

@Mitch Bailey @Luis Henrique Rodovalho THANK YOU SO MUCH FOR PROVIDING THE INFORMATION DO I MANDATORY NEED TO INCREASE THE TRANSISTOR SIZE OF CMOS SWITCH TO PASS THE ANALOG INPUT

It all depends on your load. Is it purely capacitive? Does your input is a voltage or a current?

input is voltage and i waant at least 50 micro amps as output current how do i measure the current in the out for above circuit?

Switches have on and off resistances. You must design for that. Then, there is the digital input capacitances. It depends the digital input frequency and driver.

okay @Luis Henrique Rodovalho thank you so much

isn't there a transmission gate device available in the pdk?

@Rafeeq Khan Mohammed If you plan to use high voltage on pfet transistors (like 5V) always ensure the same or higher voltage is applied on pfet bulk terminal. So you can not have AIN=5V and bulk at VDD=1.8V on the CMOS transmission gate.

@Stefan Schippers thank you