*Sidenote, adding cap at the reference voltage nodes seemed get rid of this issue. However, I am unsure if this is the most elegant solution or if it is a sound solution

A pre-amplifier before the strong arm could also help.

@carsten noted and thank you! Might you know why my VREF nodes are swinging in the first place?

You're trying to model the reference with a resistance, which is a good thing. The question should be how much resistance? Your reference voltage could be the buffered by an opamp, for example. I don't believe you would connect it directly to a bandgap reference node.

@Luis Henrique Rodovalho if I were to take the reference voltage(s) from a resistive divider, would you recommend buffering that voltage using an op-amp?

You must choose between buffering or using small resistances, so the current is larger. It's a matter of complexity. The highest voltage in the resistive ladder should be buffered, somehow. For example, if you have a bandgap voltage at 1.2 V, maybe your VREF, will be 2.4 V. You will need some kind of buffering and feedback.

I would assume it's kickback through gate capacitance of the differential pair in the StrongArm. Both the source and the drain of the differential pair in the StrongArm changes voltage during a decision.

I see. I suppose the current passes through cgd, cgs during the comparison, depending on which edge. I’m fighting it quite difficult to combat kickback noise in dynamic comparators.