Does OpenLANE support using SystemVerilog files instead of Verilog, or would it be better to use the sv2v converter?

Use sv2v

Is there any reason for that or any place where I can investigate why it's better to use sv2v?

Because yosys does not support systemverilog synthesis unless you use the paid version. You can also try to use synlig but it’s SV support is not complete. I would recommend sv2v, since it has better (though not perfect) support for standard SystemVerilog