There is irq at pin 12? The data sheet does not say that @jeffdi

Back to "caravel.py" in

caravel_mgmt_soc_litex/litex/

: There are 6 IRQs defined:

# Add 6 IRQ lines
        user_irq = platform.request("user_irq")
        for i in range(len(user_irq)):
            setattr(self.submodules,"user_irq_"+str(i),GPIOIn(user_irq[i], with_irq=True))
            self.irq.add("user_irq_"+str(i), use_loc_if_exists=True)

Three of these are the "user IRQ" signals that are defined as pins on the user project wrapper. The other three come from housekeeping: Two of them routed (if the routing is enabled) from pins GPIO 7 and 12, as you note above, and the other generated in a housekeeping register.

@Tim Edwards @Matt Venn I am not clear but can I use the gpio pin which is connected to led in eval board as interrupt? Could u pls direct me to an example

The only GPIOs that can be routed to interrupts are GPIO 7 and 12. There is a register

reg_irq_source

(memory map address

0x2620000C

) that can be used to enable the GPIOs for interrupt use. If I recall correctly, bit 0 enables GPIO 7 for IRQ, and bit 1 enables GPIO 12 for IRQ.

What which routine will be called when these interrupt trigger? Pls do u have any example code? @Tim Edwards

I am not familiar with the interrupt code for the VexRISC. But there should be examples that are run in cocotb to test the IRQ functions. Maybe @Marwan Abbas knows, or can point you to somebody who does.

12 means mproj_io 12 @Tim Edwards ?

Yes, that's right.

@Mostafa Rady is the right person to answer the question

@samarth jain you could use the functions declared here to interact with the IRQs. This is an example test for using gpio 12 as IRQ. In the example the using of the flag is optional it's the way we verified the interrupt if you need to custom what happens when the irq is triggers, update the isr function.

How to set the interrupts setting, like rising edge or falling state? @Mostafa Rady

I don't think it's possible with the current gpio setup as the high edge is the only condition to trigger the isr.

@Mostafa Rady what is interrupt priority list. If I am using SPI for communication and my interrupt on pin 12 is triggered, what will happen to the bits sent by my chip spi master? Will data get corrupted?

If I understand the question correctly, nothing would be corrupted. There is an SPI module that write and read. the cpu just send access this module registers to configure them. So as long as this spi is a master no data would be missed.